pl/math: Add vector/Neon acosh

New routine is based on a vector implementation from log1p, which has
been reused (with some modification for improved accuracy close to 0)
from Neon atanh. Accurate to 3.5 ULP.

6 files changed, 152 insertions, 45 deletions

diff --git a/pl/math/include/mathlib.h b/pl/math/include/mathlib.h
index dc2cef8..64e34d5 100644
--- a/pl/math/include/mathlib.h
+++ b/pl/math/include/mathlib.h
@@ -56,6 +56,7 @@ float __s_sinhf (float);
 float __s_tanf (float);
 float __s_tanhf (float);
 
+double __s_acosh (double);
 double __s_asinh (double);
 double __s_atan (double);
 double __s_atan2 (double, double);
@@ -84,6 +85,7 @@ typedef __attribute__((__neon_vector_type__(2))) double __f64x2_t;
 
 /* Vector functions following the base PCS.  */
 __f32x4_t __v_acoshf (__f32x4_t);
+__f64x2_t __v_acosh (__f64x2_t);
 __f32x4_t __v_asinhf (__f32x4_t);
 __f64x2_t __v_asinh (__f64x2_t);
 __f32x4_t __v_atanf (__f32x4_t);
@@ -119,6 +121,7 @@ __f64x2_t __v_tanh (__f64x2_t);
 
 /* Vector functions following the vector PCS.  */
 __vpcs __f32x4_t __vn_acoshf (__f32x4_t);
+__vpcs __f64x2_t __vn_acosh (__f64x2_t);
 __vpcs __f32x4_t __vn_asinhf (__f32x4_t);
 __vpcs __f64x2_t __vn_asinh (__f64x2_t);
 __vpcs __f32x4_t __vn_atanf (__f32x4_t);
@@ -151,6 +154,7 @@ __vpcs __f64x2_t __vn_tanh (__f64x2_t);
 
 /* Vector functions following the vector PCS using ABI names.  */
 __vpcs __f32x4_t _ZGVnN4v_acoshf (__f32x4_t);
+__vpcs __f64x2_t _ZGVnN2v_acosh (__f64x2_t);
 __vpcs __f32x4_t _ZGVnN4v_asinhf (__f32x4_t);
 __vpcs __f64x2_t _ZGVnN2v_asinh (__f64x2_t);
 __vpcs __f32x4_t _ZGVnN4v_atanf (__f32x4_t);
diff --git a/pl/math/s_acosh_3u5.c b/pl/math/s_acosh_3u5.c
new file mode 100644
index 0000000..f62cbd6
--- /dev/null
+++ b/pl/math/s_acosh_3u5.c
@@ -0,0 +1,6 @@
+/*
+ * Copyright (c) 2023, Arm Limited.
+ * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
+ */
+#define SCALAR 1
+#include "v_acosh_3u5.c"
diff --git a/pl/math/v_acosh_3u5.c b/pl/math/v_acosh_3u5.c
new file mode 100644
index 0000000..22f69d7
--- /dev/null
+++ b/pl/math/v_acosh_3u5.c
@@ -0,0 +1,51 @@
+/*
+ * Single-precision vector acosh(x) function.
+ * Copyright (c) 2023, Arm Limited.
+ * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
+ */
+
+#include "v_math.h"
+#include "pl_sig.h"
+#include "pl_test.h"
+
+#define WANT_V_LOG1P_K0_SHORTCUT 1
+#include "v_log1p_inline.h"
+
+#define BigBoundTop 0x5fe /* top12 (asuint64 (0x1p511)).  */
+
+#if V_SUPPORTED
+
+static NOINLINE VPCS_ATTR v_f64_t
+special_case (v_f64_t x)
+{
+  return v_call_f64 (acosh, x, x, v_u64 (-1));
+}
+
+/* Vector approximation for double-precision acosh, based on log1p.
+   The largest observed error is 3.02 ULP in the region where the
+   argument to log1p falls in the k=0 interval, i.e. x close to 1:
+   __v_acosh(0x1.00798aaf80739p+0) got 0x1.f2d6d823bc9dfp-5
+				  want 0x1.f2d6d823bc9e2p-5.  */
+VPCS_ATTR v_f64_t V_NAME (acosh) (v_f64_t x)
+{
+  v_u64_t itop = v_as_u64_f64 (x) >> 52;
+  v_u64_t special = v_cond_u64 ((itop - OneTop) >= (BigBoundTop - OneTop));
+
+  /* Fall back to scalar routine for all lanes if any of them are special.  */
+  if (unlikely (v_any_u64 (special)))
+    return special_case (x);
+
+  v_f64_t xm1 = x - 1;
+  v_f64_t u = xm1 * (x + 1);
+  return log1p_inline (xm1 + v_sqrt_f64 (u));
+}
+VPCS_ALIAS
+
+PL_SIG (V, D, 1, acosh, 1.0, 10.0)
+PL_TEST_ULP (V_NAME (acosh), 2.53)
+PL_TEST_EXPECT_FENV_ALWAYS (V_NAME (acosh))
+PL_TEST_INTERVAL (V_NAME (acosh), 1, 0x1p511, 90000)
+PL_TEST_INTERVAL (V_NAME (acosh), 0x1p511, inf, 10000)
+PL_TEST_INTERVAL (V_NAME (acosh), 0, 1, 1000)
+PL_TEST_INTERVAL (V_NAME (acosh), -0, -inf, 10000)
+#endif
diff --git a/pl/math/v_atanh_3u5.c b/pl/math/v_atanh_3u5.c
index ca68020..ffd6f59 100644
--- a/pl/math/v_atanh_3u5.c
+++ b/pl/math/v_atanh_3u5.c
@@ -12,56 +12,13 @@
 
 #if V_SUPPORTED
 
-#define Ln2Hi v_f64 (0x1.62e42fefa3800p-1)
-#define Ln2Lo v_f64 (0x1.ef35793c76730p-45)
-#define HfRt2Top 0x3fe6a09e00000000 /* top32(asuint64(sqrt(2)/2)) << 32.  */
-#define OneMHfRt2Top                                                           \
-  0x00095f6200000000 /* (top32(asuint64(1)) - top32(asuint64(sqrt(2)/2)))      \
-			<< 32.  */
-#define OneTop12 0x3ff
-#define BottomMask 0xffffffff
+#define WANT_V_LOG1P_K0_SHORTCUT 0
+#include "v_log1p_inline.h"
 
 #define AbsMask 0x7fffffffffffffff
 #define Half 0x3fe0000000000000
 #define One 0x3ff0000000000000
 
-#define C(i) v_f64 (__log1p_data.coeffs[i])
-
-static inline v_f64_t
-log1p_inline (v_f64_t x)
-{
-  /* Helper for calculating log(1 + x) using order-18 polynomial on a reduced
-     interval. Copied from v_log1p_2u5.c, with the following modifications:
-     - No special-case handling.
-     - Pairwise Horner instead of Estrin for improved accuracy.
-     - Slightly different recombination to reuse f2.
-     See original source for details of the algorithm.  */
-  v_f64_t m = x + 1;
-  v_u64_t mi = v_as_u64_f64 (m);
-
-  /* Decompose x + 1 into (f + 1) * 2^k, with k chosen such that f is in
-     [sqrt(2)/2, sqrt(2)].  */
-  v_u64_t u = mi + OneMHfRt2Top;
-  v_s64_t ki = v_as_s64_u64 (u >> 52) - OneTop12;
-  v_f64_t k = v_to_f64_s64 (ki);
-  v_u64_t utop = (u & 0x000fffff00000000) + HfRt2Top;
-  v_u64_t u_red = utop | (mi & BottomMask);
-  v_f64_t f = v_as_f64_u64 (u_red) - 1;
-
-  /* Correction term for round-off in f.  */
-  v_f64_t cm = (x - (m - 1)) / m;
-
-  /* Approximate log1p(f) with polynomial.  */
-  v_f64_t f2 = f * f;
-  v_f64_t p = PAIRWISE_HORNER_18 (f, f2, C);
-
-  /* Recombine log1p(x) = k*log2 + log1p(f) + c/m.  */
-  v_f64_t ylo = v_fma_f64 (k, Ln2Lo, cm);
-  v_f64_t yhi = v_fma_f64 (k, Ln2Hi, f);
-  v_f64_t y = v_fma_f64 (f2, p, ylo + yhi);
-  return y;
-}
-
 VPCS_ATTR
 NOINLINE static v_f64_t
 specialcase (v_f64_t x, v_f64_t y, v_u64_t special)
diff --git a/pl/math/v_log1p_inline.h b/pl/math/v_log1p_inline.h
new file mode 100644
index 0000000..e5c7339
--- /dev/null
+++ b/pl/math/v_log1p_inline.h
@@ -0,0 +1,77 @@
+/*
+ * Helper for vector double-precision routines which calculate log(1 + x) and do
+ * not need special-case handling
+ *
+ * Copyright (c) 2022-2023, Arm Limited.
+ * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
+ */
+#ifndef PL_MATH_V_LOG1P_INLINE_H
+#define PL_MATH_V_LOG1P_INLINE_H
+
+#include "v_math.h"
+#include "pairwise_horner.h"
+
+#define Ln2Hi v_f64 (0x1.62e42fefa3800p-1)
+#define Ln2Lo v_f64 (0x1.ef35793c76730p-45)
+#define HfRt2Top 0x3fe6a09e00000000 /* top32(asuint64(sqrt(2)/2)) << 32.  */
+#define OneMHfRt2Top                                                           \
+  0x00095f6200000000 /* (top32(asuint64(1)) - top32(asuint64(sqrt(2)/2)))      \
+			<< 32.  */
+#define OneTop 0x3ff
+#define BottomMask 0xffffffff
+#define BigBoundTop 0x5fe /* top12 (asuint64 (0x1p511)).  */
+
+#define C(i) v_f64 (__log1p_data.coeffs[i])
+
+static inline v_f64_t
+log1p_inline (v_f64_t x)
+{
+  /* Helper for calculating log(x + 1). Copied from v_log1p_2u5.c, with several
+     modifications:
+     - No special-case handling - this should be dealt with by the caller.
+     - Pairwise Horner polynomial evaluation for improved accuracy.
+     - Optionally simulate the shortcut for k=0, used in the scalar routine,
+       using v_sel, for improved accuracy when the argument to log1p is close to
+       0. This feature is enabled by defining WANT_V_LOG1P_K0_SHORTCUT as 1 in
+       the source of the caller before including this file.
+     See v_log1pf_2u1.c for details of the algorithm.  */
+  v_f64_t m = x + 1;
+  v_u64_t mi = v_as_u64_f64 (m);
+  v_u64_t u = mi + OneMHfRt2Top;
+
+  v_s64_t ki = v_as_s64_u64 (u >> 52) - OneTop;
+  v_f64_t k = v_to_f64_s64 (ki);
+
+  /* Reduce x to f in [sqrt(2)/2, sqrt(2)].  */
+  v_u64_t utop = (u & 0x000fffff00000000) + HfRt2Top;
+  v_u64_t u_red = utop | (mi & BottomMask);
+  v_f64_t f = v_as_f64_u64 (u_red) - 1;
+
+  /* Correction term c/m.  */
+  v_f64_t cm = (x - (m - 1)) / m;
+
+#ifndef WANT_V_LOG1P_K0_SHORTCUT
+#error                                                                         \
+  "Cannot use v_log1p_inline.h without specifying whether you need the k0 shortcut for greater accuracy close to 0"
+#elif WANT_V_LOG1P_K0_SHORTCUT
+  /* Shortcut if k is 0 - set correction term to 0 and f to x. The result is
+     that the approximation is solely the polynomial. */
+  v_u64_t k0 = k == 0;
+  if (unlikely (v_any_u64 (k0)))
+    {
+      cm = v_sel_f64 (k0, v_f64 (0), cm);
+      f = v_sel_f64 (k0, x, f);
+    }
+#endif
+
+  /* Approximate log1p(f) on the reduced input using a polynomial.  */
+  v_f64_t f2 = f * f;
+  v_f64_t p = PAIRWISE_HORNER_18 (f, f2, C);
+
+  /* Assemble log1p(x) = k * log2 + log1p(f) + c/m.  */
+  v_f64_t ylo = v_fma_f64 (k, Ln2Lo, cm);
+  v_f64_t yhi = v_fma_f64 (k, Ln2Hi, f);
+  return v_fma_f64 (f2, p, ylo + yhi);
+}
+
+#endif // PL_MATH_V_LOG1P_INLINE_H
diff --git a/pl/math/vn_acosh_3u5.c b/pl/math/vn_acosh_3u5.c
new file mode 100644
index 0000000..649735b
--- /dev/null
+++ b/pl/math/vn_acosh_3u5.c
@@ -0,0 +1,12 @@
+/*
+ * AdvSIMD vector PCS variant of __v_acosh.
+ *
+ * Copyright (c) 2023, Arm Limited.
+ * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
+ */
+#include "include/mathlib.h"
+#ifdef __vpcs
+#define VPCS 1
+#define VPCS_ALIAS PL_ALIAS (__vn_acosh, _ZGVnN2v_acosh)
+#include "v_acosh_3u5.c"
+#endif