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| author | Joe Ramsay <Joe.Ramsay@arm.com> | 2022-12-19 12:45:41 +0000 |
|---|---|---|
| committer | Joe Ramsay <joe.ramsay@arm.com> | 2022-12-19 12:45:41 +0000 |
| commit | a5fc3ed57ba4bc6df2e582f6a51c5fcc8e4459cd (patch) | |
| tree | 1cc08e02fb7bebcb62fd3512be7696c2f3c52af6 | |
| parent | d05594e6718e6d86959c823bea4f019dea878bcb (diff) | |
| download | arm-optimized-routines-a5fc3ed57ba4bc6df2e582f6a51c5fcc8e4459cd.tar.gz | |
pl/math: Update ULP threshold for Neon asinh
New max observed - updated filenames, comments and runulp threshold.
| -rw-r--r-- | pl/math/s_asinh_3u5.c (renamed from pl/math/s_asinh_2u5.c) | 2 | ||||
| -rw-r--r-- | pl/math/v_asinh_3u5.c (renamed from pl/math/v_asinh_2u5.c) | 8 | ||||
| -rw-r--r-- | pl/math/vn_asinh_3u5.c (renamed from pl/math/vn_asinh_2u5.c) | 2 |
3 files changed, 6 insertions, 6 deletions
diff --git a/pl/math/s_asinh_2u5.c b/pl/math/s_asinh_3u5.c index 6da30bd..d767100 100644 --- a/pl/math/s_asinh_2u5.c +++ b/pl/math/s_asinh_3u5.c @@ -3,4 +3,4 @@ * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception */ #define SCALAR 1 -#include "v_asinh_2u5.c" +#include "v_asinh_3u5.c" diff --git a/pl/math/v_asinh_2u5.c b/pl/math/v_asinh_3u5.c index 04d369d..5294a3c 100644 --- a/pl/math/v_asinh_2u5.c +++ b/pl/math/v_asinh_3u5.c @@ -84,10 +84,10 @@ log_inline (v_f64_t x) asinh(x) = sign(x) * log(|x| + sqrt(x^2 + 1) if |x| >= 1 = sign(x) * (|x| + |x|^3 * P(x^2)) otherwise where log(x) is an optimized log approximation, and P(x) is a polynomial - shared with the scalar routine. The greatest observed error 2.03 ULP, in + shared with the scalar routine. The greatest observed error 3.29 ULP, in |x| >= 1: - __v_asinh(-0x1.00094e0f39574p+0) got -0x1.c3508eb6a681ep-1 - want -0x1.c3508eb6a682p-1. */ + __v_asinh(0x1.2cd9d717e2c9bp+0) got 0x1.ffffcfd0e234fp-1 + want 0x1.ffffcfd0e2352p-1. */ VPCS_ATTR v_f64_t V_NAME (asinh) (v_f64_t x) { v_u64_t ix = v_as_u64_f64 (x); @@ -155,7 +155,7 @@ VPCS_ATTR v_f64_t V_NAME (asinh) (v_f64_t x) VPCS_ALIAS PL_SIG (V, D, 1, asinh, -10.0, 10.0) -PL_TEST_ULP (V_NAME (asinh), 1.54) +PL_TEST_ULP (V_NAME (asinh), 2.80) PL_TEST_EXPECT_FENV (V_NAME (asinh), WANT_SIMD_EXCEPT) /* Test vector asinh 3 times, with control lane < 1, > 1 and special. Ensures the v_sel is choosing the right option in all cases. */ diff --git a/pl/math/vn_asinh_2u5.c b/pl/math/vn_asinh_3u5.c index e349530..e2f3aeb 100644 --- a/pl/math/vn_asinh_2u5.c +++ b/pl/math/vn_asinh_3u5.c @@ -8,5 +8,5 @@ #ifdef __vpcs #define VPCS 1 #define VPCS_ALIAS PL_ALIAS (__vn_asinh, _ZGVnN2v_asinh) -#include "v_asinh_2u5.c" +#include "v_asinh_3u5.c" #endif |