diff options
Diffstat (limited to 'pl/math/v_asinh_2u5.c')
| -rw-r--r-- | pl/math/v_asinh_2u5.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/pl/math/v_asinh_2u5.c b/pl/math/v_asinh_2u5.c index 4eeec4a..04d369d 100644 --- a/pl/math/v_asinh_2u5.c +++ b/pl/math/v_asinh_2u5.c @@ -98,19 +98,19 @@ VPCS_ATTR v_f64_t V_NAME (asinh) (v_f64_t x) v_u64_t gt1 = v_cond_u64 (top12 >= OneTop); v_u64_t special = v_cond_u64 (top12 >= HugeBound); -#if WANT_ERRNO +#if WANT_SIMD_EXCEPT v_u64_t tiny = v_cond_u64 (top12 < TinyBound); special |= tiny; #endif /* Option 1: |x| >= 1. Compute asinh(x) according by asinh(x) = log(x + sqrt(x^2 + 1)). - If WANT_ERRNO is enabled, sidestep special values, which will overflow, by - setting special lanes to 1. These will be fixed later. */ + If WANT_SIMD_EXCEPT is enabled, sidestep special values, which will + overflow, by setting special lanes to 1. These will be fixed later. */ v_f64_t option_1 = v_f64 (0); if (likely (v_any_u64 (gt1))) { -#if WANT_ERRNO +#if WANT_SIMD_EXCEPT v_f64_t xm = v_sel_f64 (special, v_f64 (1), ax); #else v_f64_t xm = ax; @@ -120,16 +120,16 @@ VPCS_ATTR v_f64_t V_NAME (asinh) (v_f64_t x) /* Option 2: |x| < 1. Compute asinh(x) using a polynomial. - If WANT_ERRNO is enabled, sidestep special lanes, which will overflow, and - tiny lanes, which will underflow, by setting them to 0. They will be fixed - later, either by selecting x or falling back to the scalar special-case. - The largest observed error in this region is 1.47 ULPs: + If WANT_SIMD_EXCEPT is enabled, sidestep special lanes, which will + overflow, and tiny lanes, which will underflow, by setting them to 0. They + will be fixed later, either by selecting x or falling back to the scalar + special-case. The largest observed error in this region is 1.47 ULPs: __v_asinh(0x1.fdfcd00cc1e6ap-1) got 0x1.c1d6bf874019bp-1 want 0x1.c1d6bf874019cp-1. */ v_f64_t option_2 = v_f64 (0); if (likely (v_any_u64 (~gt1))) { -#if WANT_ERRNO +#if WANT_SIMD_EXCEPT ax = v_sel_f64 (tiny | gt1, v_f64 (0), ax); #endif v_f64_t x2 = ax * ax; @@ -138,7 +138,7 @@ VPCS_ATTR v_f64_t V_NAME (asinh) (v_f64_t x) v_f64_t z8 = z4 * z4; v_f64_t p = ESTRIN_17 (x2, z2, z4, z8, z8 * z8, C); option_2 = v_fma_f64 (p, x2 * ax, ax); -#if WANT_ERRNO +#if WANT_SIMD_EXCEPT option_2 = v_sel_f64 (tiny, x, option_2); #endif } @@ -156,7 +156,7 @@ VPCS_ALIAS PL_SIG (V, D, 1, asinh, -10.0, 10.0) PL_TEST_ULP (V_NAME (asinh), 1.54) -PL_TEST_EXPECT_FENV (V_NAME (asinh), WANT_ERRNO) +PL_TEST_EXPECT_FENV (V_NAME (asinh), WANT_SIMD_EXCEPT) /* Test vector asinh 3 times, with control lane < 1, > 1 and special. Ensures the v_sel is choosing the right option in all cases. */ #define V_ASINH_INTERVAL(lo, hi, n) \ |