diff options
| author | Icenowy Zheng <icenowy@sipeed.com> | 2021-07-22 09:35:19 +0800 |
|---|---|---|
| committer | Icenowy Zheng <icenowy@aosc.io> | 2021-08-25 00:33:59 +0800 |
| commit | 080939f9244f1717c7bb4c32ff30fb72032d36fb (patch) | |
| tree | 0f1fc7589dfee2b37bdc03805b02125d63b1f3f5 | |
| parent | 86a7429e477786dad6fab002538aef825f4ca35a (diff) | |
| download | arm-trusted-firmware-080939f9244f1717c7bb4c32ff30fb72032d36fb.tar.gz | |
refactor(plat/allwinner): allow new AA64nAA32 position
In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register
called "General Control Register0" in the manual rather than the
"Cluster 0 Control Register0" in older SoCs.
Now the position of AA64nAA32 (reg and bit offset) is defined in a few
macros instead assumed to be at bit offset 24 of
SUNXI_CPUCFG_CLS_CTRL_REG0.
Change-Id: I933d00b9a914bf7103e3a9dadbc6d7be1a409668
Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
| -rw-r--r-- | plat/allwinner/common/sunxi_cpu_ops.c | 3 | ||||
| -rw-r--r-- | plat/allwinner/sun50i_a64/include/sunxi_cpucfg.h | 3 | ||||
| -rw-r--r-- | plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h | 3 | ||||
| -rw-r--r-- | plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h | 3 |
4 files changed, 11 insertions, 1 deletions
diff --git a/plat/allwinner/common/sunxi_cpu_ops.c b/plat/allwinner/common/sunxi_cpu_ops.c index 8a29dbbd5..46e7090ab 100644 --- a/plat/allwinner/common/sunxi_cpu_ops.c +++ b/plat/allwinner/common/sunxi_cpu_ops.c @@ -76,7 +76,8 @@ void sunxi_cpu_on(u_register_t mpidr) /* Assert CPU power-on reset */ mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core)); /* Set CPU to start in AArch64 mode */ - mmio_setbits_32(SUNXI_CPUCFG_CLS_CTRL_REG0(cluster), BIT(24 + core)); + mmio_setbits_32(SUNXI_AA64nAA32_REG(cluster), + BIT(SUNXI_AA64nAA32_OFFSET + core)); /* Apply power to the CPU */ sunxi_cpu_enable_power(cluster, core); /* Release the core output clamps */ diff --git a/plat/allwinner/sun50i_a64/include/sunxi_cpucfg.h b/plat/allwinner/sun50i_a64/include/sunxi_cpucfg.h index c3eeadbaa..aed358572 100644 --- a/plat/allwinner/sun50i_a64/include/sunxi_cpucfg.h +++ b/plat/allwinner/sun50i_a64/include/sunxi_cpucfg.h @@ -33,4 +33,7 @@ #define SUNXI_R_CPUCFG_SS_ENTRY_REG (SUNXI_R_CPUCFG_BASE + 0x01a8) #define SUNXI_R_CPUCFG_HP_FLAG_REG (SUNXI_R_CPUCFG_BASE + 0x01ac) +#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0 +#define SUNXI_AA64nAA32_OFFSET 24 + #endif /* SUNXI_CPUCFG_H */ diff --git a/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h b/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h index a2b94af13..5bfda5db9 100644 --- a/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h +++ b/plat/allwinner/sun50i_h6/include/sunxi_cpucfg.h @@ -29,4 +29,7 @@ #define SUNXI_PWR_SW_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0140) #define SUNXI_CONFIG_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0144) +#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0 +#define SUNXI_AA64nAA32_OFFSET 24 + #endif /* SUNXI_CPUCFG_H */ diff --git a/plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h b/plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h index a63755415..dab663b6b 100644 --- a/plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h +++ b/plat/allwinner/sun50i_h616/include/sunxi_cpucfg.h @@ -29,4 +29,7 @@ #define SUNXI_PWR_SW_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0140) #define SUNXI_CONFIG_DELAY_REG (SUNXI_R_CPUCFG_BASE + 0x0144) +#define SUNXI_AA64nAA32_REG SUNXI_CPUCFG_CLS_CTRL_REG0 +#define SUNXI_AA64nAA32_OFFSET 24 + #endif /* SUNXI_CPUCFG_H */ |