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author | Madhukar Pappireddy <madhukar.pappireddy@arm.com> | 2021-09-03 21:31:00 +0200 |
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committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2021-09-03 21:31:00 +0200 |
commit | b7942a91b850aba426cfc2084fb6eaef8b864451 (patch) | |
tree | 93bb4f59f562f3a91d29008a7769014f93f02980 | |
parent | 81de40f23b8a9302991d4ebd42c38b88a45511da (diff) | |
parent | 4618b2bfa7116371a5785a32f69ef2ea928f7cb7 (diff) | |
download | arm-trusted-firmware-b7942a91b850aba426cfc2084fb6eaef8b864451.tar.gz |
Merge changes from topic "erratas" into integration
* changes:
errata: workaround for Neoverse N2 erratum 2025414
errata: workaround for Neoverse N2 erratum 2067956
-rw-r--r-- | docs/design/cpu-specific-build-macros.rst | 8 | ||||
-rw-r--r-- | include/lib/cpus/aarch64/neoverse_n2.h | 9 | ||||
-rw-r--r-- | lib/cpus/aarch64/neoverse_n2.S | 83 | ||||
-rw-r--r-- | lib/cpus/cpu-ops.mk | 16 |
4 files changed, 106 insertions, 10 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index b5092c45c..ff8a66df9 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -381,6 +381,14 @@ For Cortex-A710, the following errata build flags are defined : Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and r2p0 of the CPU. It is still open. +For Neoverse N2, the following errata build flags are defined : + +- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 + CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. + +- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 + CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. + DSU Errata Workarounds ---------------------- diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h index 7cbd8c17b..68f6a40c4 100644 --- a/include/lib/cpus/aarch64/neoverse_n2.h +++ b/include/lib/cpus/aarch64/neoverse_n2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,10 +21,17 @@ ******************************************************************************/ #define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) +#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ +#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 +#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) + +/******************************************************************************* + * CPU Auxiliary Control register 2 specific definitions. + ******************************************************************************/ #define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 #define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index 44db0b3a3..a745ca5d6 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -61,9 +61,62 @@ func check_errata_2002655 b cpu_rev_var_ls endfunc check_errata_2002655 - /* ------------------------------------------------- +/* --------------------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2067956. + * This applies to revision r0p0 of Neoverse N2 and is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * --------------------------------------------------------------- + */ +func errata_n2_2067956_wa + /* Compare x0 against revision r0p0 */ + mov x17, x30 + bl check_errata_2067956 + cbz x0, 1f + mrs x1, NEOVERSE_N2_CPUACTLR_EL1 + orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46 + msr NEOVERSE_N2_CPUACTLR_EL1, x1 +1: + ret x17 +endfunc errata_n2_2067956_wa + +func check_errata_2067956 + /* Applies to r0p0 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2067956 + +/* --------------------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2025414. + * This applies to revision r0p0 of Neoverse N2 and is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * --------------------------------------------------------------- + */ +func errata_n2_2025414_wa + /* Compare x0 against revision r0p0 */ + mov x17, x30 + bl check_errata_2025414 + cbz x0, 1f + mrs x1, NEOVERSE_N2_CPUECTLR_EL1 + orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT + msr NEOVERSE_N2_CPUECTLR_EL1, x1 + +1: + ret x17 +endfunc errata_n2_2025414_wa + +func check_errata_2025414 + /* Applies to r0p0 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2025414 + + /* ------------------------------------------- * The CPU Ops reset function for Neoverse N2. - * ------------------------------------------------- + * ------------------------------------------- */ func neoverse_n2_reset_func mov x19, x30 @@ -81,6 +134,16 @@ func neoverse_n2_reset_func orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 msr NEOVERSE_N2_CPUACTLR2_EL1, x0 +#if ERRATA_N2_2067956 + mov x0, x18 + bl errata_n2_2067956_wa +#endif + +#if ERRATA_N2_2025414 + mov x0, x18 + bl errata_n2_2025414_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, cptr_el3 @@ -97,9 +160,9 @@ func neoverse_n2_reset_func #if NEOVERSE_Nx_EXTERNAL_LLC /* Some systems may have External LLC, core needs to be made aware */ - mrs x0, NEOVERSE_N2_CPUECTLR_EL1 - orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT - msr NEOVERSE_N2_CPUECTLR_EL1, x0 + mrs x0, NEOVERSE_N2_CPUECTLR_EL1 + orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT + msr NEOVERSE_N2_CPUECTLR_EL1, x0 #endif bl cpu_get_rev_var @@ -111,14 +174,14 @@ func neoverse_n2_reset_func #endif isb - ret x19 + ret x19 endfunc neoverse_n2_reset_func func neoverse_n2_core_pwr_dwn - /* --------------------------------------------- + /* --------------------------------------------------- * Enable CPU power down bit in power control register * No need to do cache maintenance here. - * --------------------------------------------- + * --------------------------------------------------- */ mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1 orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT @@ -142,6 +205,8 @@ func neoverse_n2_errata_report * checking functions of each errata. */ report_errata ERRATA_N2_2002655, neoverse_n2, 2002655 + report_errata ERRATA_N2_2067956, neoverse_n2, 2067956 + report_errata ERRATA_N2_2025414, neoverse_n2, 2025414 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index ab50933c8..8a2dd462c 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -425,6 +425,14 @@ ERRATA_A710_1987031 ?=0 # to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. ERRATA_A710_2081180 ?=0 +# Flag to apply erratum 2067956 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu and is still open. +ERRATA_N2_2067956 ?=0 + +# Flag to apply erratum 2025414 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu and is still open. +ERRATA_N2_2025414 ?=0 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. ERRATA_DSU_798953 ?=0 @@ -782,6 +790,14 @@ $(eval $(call add_define,ERRATA_A710_1987031)) $(eval $(call assert_boolean,ERRATA_A710_2081180)) $(eval $(call add_define,ERRATA_A710_2081180)) +# Process ERRATA_N2_2067956 flag +$(eval $(call assert_boolean,ERRATA_N2_2067956)) +$(eval $(call add_define,ERRATA_N2_2067956)) + +# Process ERRATA_N2_2025414 flag +$(eval $(call assert_boolean,ERRATA_N2_2025414)) +$(eval $(call add_define,ERRATA_N2_2025414)) + # Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953)) |