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author | nayanpatel-arm <nayankumar.patel@arm.com> | 2021-09-28 09:46:45 -0700 |
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committer | nayanpatel-arm <nayankumar.patel@arm.com> | 2021-10-01 12:01:20 -0700 |
commit | ef8f0c52ddf83e815a029319971682d7a26b6a6f (patch) | |
tree | 36e393a1ee078d618f04aa431e96d389573eb83c | |
parent | ab5964aadcf090c816804a798c0d49bc0c9b5183 (diff) | |
download | arm-trusted-firmware-ef8f0c52ddf83e815a029319971682d7a26b6a6f.tar.gz |
fix(errata): workaround for Neoverse-N2 erratum 2138953
Neoverse-N2 erratum 2138953 is a Cat B erratum that applies to
revision r0p0 of CPU. It is still open. The workaround
is to write the value 4'b1001 to the PF_MODE bits in the
IMP_CPUECTLR2_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: Ife0a4bece7ccf83cc99c1d5f5b5a43084bb69d64
-rw-r--r-- | docs/design/cpu-specific-build-macros.rst | 3 | ||||
-rw-r--r-- | include/lib/cpus/aarch64/neoverse_n2.h | 32 | ||||
-rw-r--r-- | lib/cpus/aarch64/neoverse_n2.S | 37 | ||||
-rw-r--r-- | lib/cpus/cpu-ops.mk | 8 |
4 files changed, 67 insertions, 13 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index bde6d97e6..9676ae787 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -403,6 +403,9 @@ For Neoverse N2, the following errata build flags are defined : - ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. +- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2 + CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. + DSU Errata Workarounds ---------------------- diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h index 948f96511..f414cb53c 100644 --- a/include/lib/cpus/aarch64/neoverse_n2.h +++ b/include/lib/cpus/aarch64/neoverse_n2.h @@ -8,37 +8,45 @@ #define NEOVERSE_N2_H /* Neoverse N2 ID register for revision r0p0 */ -#define NEOVERSE_N2_MIDR U(0x410FD490) +#define NEOVERSE_N2_MIDR U(0x410FD490) /******************************************************************************* * CPU Power control register ******************************************************************************/ -#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 -#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) +#define NEOVERSE_N2_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define NEOVERSE_N2_CORE_PWRDN_EN_BIT (ULL(1) << 0) /******************************************************************************* * CPU Extended Control register specific definitions. ******************************************************************************/ -#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 -#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) -#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) +#define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 +#define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) +#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 -#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) +#define NEOVERSE_N2_CPUACTLR_EL1 S3_0_C15_C1_0 +#define NEOVERSE_N2_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) /******************************************************************************* * CPU Auxiliary Control register 2 specific definitions. ******************************************************************************/ -#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 -#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) +#define NEOVERSE_N2_CPUACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2) /******************************************************************************* * CPU Auxiliary Control register 5 specific definitions. ******************************************************************************/ -#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 -#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) +#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0 +#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_N2_CPUECTLR2_EL1 S3_0_C15_C1_5 +#define NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) +#define CPUECTLR2_EL1_PF_MODE_LSB U(11) +#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) #endif /* NEOVERSE_N2_H */ diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index 9e7bbf7e6..330cc596a 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -183,6 +183,35 @@ func check_errata_2138956 b cpu_rev_var_ls endfunc check_errata_2138956 +/* -------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2138953. + * This applies to revision r0p0 of Neoverse N2. it is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * -------------------------------------------------- + */ +func errata_n2_2138953_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2138953 + cbz x0, 1f + + /* Apply instruction patching sequence */ + mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 + mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV + bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH + msr NEOVERSE_N2_CPUECTLR2_EL1, x1 +1: + ret x17 +endfunc errata_n2_2138953_wa + +func check_errata_2138953 + /* Applies to r0p0 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2138953 + /* ------------------------------------------- * The CPU Ops reset function for Neoverse N2. * ------------------------------------------- @@ -224,6 +253,11 @@ func neoverse_n2_reset_func bl errata_n2_2138956_wa #endif +#if ERRATA_N2_2138953 + mov x0, x18 + bl errata_n2_2138953_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, cptr_el3 @@ -287,8 +321,9 @@ func neoverse_n2_errata_report report_errata ERRATA_N2_2002655, neoverse_n2, 2002655 report_errata ERRATA_N2_2067956, neoverse_n2, 2067956 report_errata ERRATA_N2_2025414, neoverse_n2, 2025414 - report_errata ERRATA_N2_2189731, neoverse_n2, 2189731 + report_errata ERRATA_N2_2189731, neoverse_n2, 2189731 report_errata ERRATA_N2_2138956, neoverse_n2, 2138956 + report_errata ERRATA_N2_2138953, neoverse_n2, 2138953 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 6103a5a7b..1d470e20b 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -441,6 +441,10 @@ ERRATA_N2_2189731 ?=0 # to revision r0p0 of the Neoverse N2 cpu and is still open. ERRATA_N2_2138956 ?=0 +# Flag to apply erratum 2138953 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu and is still open. +ERRATA_N2_2138953 ?=0 + # Flag to apply erratum 2055002 workaround during reset. This erratum applies # to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open. ERRATA_A710_2055002 ?=0 @@ -822,6 +826,10 @@ $(eval $(call add_define,ERRATA_N2_2189731)) $(eval $(call assert_boolean,ERRATA_N2_2138956)) $(eval $(call add_define,ERRATA_N2_2138956)) +# Process ERRATA_N2_2138953 flag +$(eval $(call assert_boolean,ERRATA_N2_2138953)) +$(eval $(call add_define,ERRATA_N2_2138953)) + # Process ERRATA_A710_2055002 flag $(eval $(call assert_boolean,ERRATA_A710_2055002)) $(eval $(call add_define,ERRATA_A710_2055002)) |