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author | Bipin Ravi <bipin.ravi@arm.com> | 2021-03-31 10:10:27 -0500 |
---|---|---|
committer | Bipin Ravi <bipin.ravi@arm.com> | 2021-09-02 11:00:13 -0500 |
commit | 4618b2bfa7116371a5785a32f69ef2ea928f7cb7 (patch) | |
tree | 163376a7e9edf9fbadbc27c0512e849e51e45332 | |
parent | 65e04f27d42c5eccdb3893e41e25363f396e42ed (diff) | |
download | arm-trusted-firmware-4618b2bfa7116371a5785a32f69ef2ea928f7cb7.tar.gz |
errata: workaround for Neoverse N2 erratum 2025414
Neoverse N2 erratum 2025414 is a Cat B erratum that applies to
revision r0p0 and is still open. The workaround is to set
CPUECLTR_EL1[8] to 1 which disables store issue prefetching.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1982442/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: Ia1c63fb93a1bdb1c3f4cf019a197b2a59233885a
-rw-r--r-- | docs/design/cpu-specific-build-macros.rst | 3 | ||||
-rw-r--r-- | include/lib/cpus/aarch64/neoverse_n2.h | 3 | ||||
-rw-r--r-- | lib/cpus/aarch64/neoverse_n2.S | 43 | ||||
-rw-r--r-- | lib/cpus/cpu-ops.mk | 8 |
4 files changed, 51 insertions, 6 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 1f998922b..7cda5acd2 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -383,6 +383,9 @@ For Neoverse N2, the following errata build flags are defined : - ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. +- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2 + CPU. This needs to be enabled for revision r0p0 of the CPU and is still open. + DSU Errata Workarounds ---------------------- diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h index a7211d218..68f6a40c4 100644 --- a/include/lib/cpus/aarch64/neoverse_n2.h +++ b/include/lib/cpus/aarch64/neoverse_n2.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -21,6 +21,7 @@ ******************************************************************************/ #define NEOVERSE_N2_CPUECTLR_EL1 S3_0_C15_C1_4 #define NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) +#define NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) /******************************************************************************* * CPU Auxiliary Control register specific definitions. diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index 1ab5412b1..a745ca5d6 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020, Arm Limited. All rights reserved. + * Copyright (c) 2020-2021, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -87,9 +87,36 @@ func check_errata_2067956 b cpu_rev_var_ls endfunc check_errata_2067956 - /* ------------------------------------------------- +/* --------------------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2025414. + * This applies to revision r0p0 of Neoverse N2 and is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * --------------------------------------------------------------- + */ +func errata_n2_2025414_wa + /* Compare x0 against revision r0p0 */ + mov x17, x30 + bl check_errata_2025414 + cbz x0, 1f + mrs x1, NEOVERSE_N2_CPUECTLR_EL1 + orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT + msr NEOVERSE_N2_CPUECTLR_EL1, x1 + +1: + ret x17 +endfunc errata_n2_2025414_wa + +func check_errata_2025414 + /* Applies to r0p0 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2025414 + + /* ------------------------------------------- * The CPU Ops reset function for Neoverse N2. - * ------------------------------------------------- + * ------------------------------------------- */ func neoverse_n2_reset_func mov x19, x30 @@ -112,6 +139,11 @@ func neoverse_n2_reset_func bl errata_n2_2067956_wa #endif +#if ERRATA_N2_2025414 + mov x0, x18 + bl errata_n2_2025414_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, cptr_el3 @@ -146,10 +178,10 @@ func neoverse_n2_reset_func endfunc neoverse_n2_reset_func func neoverse_n2_core_pwr_dwn - /* --------------------------------------------- + /* --------------------------------------------------- * Enable CPU power down bit in power control register * No need to do cache maintenance here. - * --------------------------------------------- + * --------------------------------------------------- */ mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1 orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT @@ -174,6 +206,7 @@ func neoverse_n2_errata_report */ report_errata ERRATA_N2_2002655, neoverse_n2, 2002655 report_errata ERRATA_N2_2067956, neoverse_n2, 2067956 + report_errata ERRATA_N2_2025414, neoverse_n2, 2025414 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index b8576e9b5..f93aecdd9 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -425,6 +425,10 @@ ERRATA_A710_2081180 ?=0 # to revision r0p0 of the Neoverse N2 cpu and is still open. ERRATA_N2_2067956 ?=0 +# Flag to apply erratum 2025414 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu and is still open. +ERRATA_N2_2025414 ?=0 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. ERRATA_DSU_798953 ?=0 @@ -782,6 +786,10 @@ $(eval $(call add_define,ERRATA_A710_2081180)) $(eval $(call assert_boolean,ERRATA_N2_2067956)) $(eval $(call add_define,ERRATA_N2_2067956)) +# Process ERRATA_N2_2025414 flag +$(eval $(call assert_boolean,ERRATA_N2_2025414)) +$(eval $(call add_define,ERRATA_N2_2025414)) + # Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953)) |