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author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2020-01-17 13:45:14 +0900 |
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committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2020-01-24 22:34:25 +0900 |
commit | d974301d221762a7a0c24bf1d682fa8fe198a83d (patch) | |
tree | c96296e6545a2f953d659cb074d7b45dabcf2c09 /bl32 | |
parent | 69af7fcf99bcce85ed218c97df0b76c377b3ed16 (diff) | |
download | arm-trusted-firmware-d974301d221762a7a0c24bf1d682fa8fe198a83d.tar.gz |
TSP: add PIE support
This implementation simply mimics that of BL31.
Change-Id: Ibbaa4ca012d38ac211c52b0b3e97449947160e07
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'bl32')
-rw-r--r-- | bl32/tsp/aarch64/tsp_entrypoint.S | 22 | ||||
-rw-r--r-- | bl32/tsp/tsp.ld.S | 40 |
2 files changed, 60 insertions, 2 deletions
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 1d3ec21a7..ebc5c2c3d 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -1,9 +1,11 @@ /* - * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ +#include <platform_def.h> + #include <arch.h> #include <asm_macros.S> #include <bl32/tsp/tsp.h> @@ -46,6 +48,24 @@ func tsp_entrypoint _align=3 +#if ENABLE_PIE + /* + * ------------------------------------------------------------ + * If PIE is enabled fixup the Global descriptor Table only + * once during primary core cold boot path. + * + * Compile time base address, required for fixup, is calculated + * using "pie_fixup" label present within first page. + * ------------------------------------------------------------ + */ + pie_fixup: + ldr x0, =pie_fixup + and x0, x0, #~(PAGE_SIZE - 1) + mov_imm x1, (BL32_LIMIT - BL32_BASE) + add x1, x1, x0 + bl fixup_gdt_reloc +#endif /* ENABLE_PIE */ + /* --------------------------------------------- * Set the exception vector to something sane. * --------------------------------------------- diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S index e9a1df168..592e24557 100644 --- a/bl32/tsp/tsp.ld.S +++ b/bl32/tsp/tsp.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -36,6 +36,17 @@ SECTIONS .rodata . : { __RODATA_START__ = .; *(.rodata*) + + /* + * Keep the .got section in the RO section as it is patched + * prior to enabling the MMU and having the .got in RO is better for + * security. GOT is a table of addresses so ensure 8-byte alignment. + */ + . = ALIGN(8); + __GOT_START__ = .; + *(.got) + __GOT_END__ = .; + . = ALIGN(PAGE_SIZE); __RODATA_END__ = .; } >RAM @@ -45,7 +56,19 @@ SECTIONS *tsp_entrypoint.o(.text*) *(.text*) *(.rodata*) + + /* + * Keep the .got section in the RO section as it is patched + * prior to enabling the MMU and having the .got in RO is better for + * security. GOT is a table of addresses so ensure 8-byte alignment. + */ + . = ALIGN(8); + __GOT_START__ = .; + *(.got) + __GOT_END__ = .; + *(.vectors) + __RO_END_UNALIGNED__ = .; /* * Memory page(s) mapped to this section will be marked as @@ -69,6 +92,17 @@ SECTIONS __DATA_END__ = .; } >RAM + /* + * .rela.dyn needs to come after .data for the read-elf utility to parse + * this section correctly. Ensure 8-byte alignment so that the fields of + * RELA data structure are aligned. + */ + . = ALIGN(8); + __RELA_START__ = .; + .rela.dyn . : { + } >RAM + __RELA_END__ = .; + #ifdef TSP_PROGBITS_LIMIT ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.") #endif @@ -129,6 +163,10 @@ SECTIONS __RW_END__ = .; __BL32_END__ = .; + /DISCARD/ : { + *(.dynsym .dynstr .hash .gnu.hash) + } + __BSS_SIZE__ = SIZEOF(.bss); #if USE_COHERENT_MEM __COHERENT_RAM_UNALIGNED_SIZE__ = |