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| author | Bipin Ravi <bipin.ravi@arm.com> | 2021-03-31 18:45:55 -0500 |
|---|---|---|
| committer | Bipin Ravi <bipin.ravi@arm.com> | 2021-09-03 15:44:56 -0500 |
| commit | afc2ed63f9c83a3b7408d804cbe22f02d34d075d (patch) | |
| tree | daf947db21682ae911e9b73636ec51ae96e92e0a /docs/design | |
| parent | 213afde907a375f4f28ac1843b633ca83887f174 (diff) | |
| download | arm-trusted-firmware-afc2ed63f9c83a3b7408d804cbe22f02d34d075d.tar.gz | |
errata: workaround for Cortex-A710 erratum 2017096
Cortex-A710 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to
set CPUECLTR_EL1[8] to 1 which disables store issue prefetching.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If5f61ec30dbc2fab7f2c68663996057086e374e3
Diffstat (limited to 'docs/design')
| -rw-r--r-- | docs/design/cpu-specific-build-macros.rst | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 5a07cb79f..18f5449ed 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -382,6 +382,11 @@ For Cortex-A710, the following errata build flags are defined : Cortex-A710 CPU. This needs to be enabled for revisions r1p0, r2p0 of the CPU and is still open. +- ``ERRATA_A710_2017096``: This applies errata 2017096 workaround to + Cortex-A710 CPU. This needs to be enabled for revisions r0p0, r1p0 and r2p0 + of the CPU and is still open. + + For Neoverse N2, the following errata build flags are defined : - ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2 |