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| author | Grzegorz Jaszczyk <jaz@semihalf.com> | 2018-12-20 17:13:19 +0100 |
|---|---|---|
| committer | Marcin Wojtas <mw@semihalf.com> | 2020-06-07 00:06:03 +0200 |
| commit | dc402531eff62ca54c3f9f360be50c1c113d16f9 (patch) | |
| tree | 614e1bf401628018f9a16eb6589bcba6b5600e8c /drivers/marvell/ap807_clocks_init.c | |
| parent | 613bbde09e48874658af5a00612fe2a0b0388523 (diff) | |
| download | arm-trusted-firmware-dc402531eff62ca54c3f9f360be50c1c113d16f9.tar.gz | |
plat: marvell: add support for PLL 2.2GHz mode
Change-Id: Icb8fe14417665d6aadd5a5ee2b77547b4ef78773
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Diffstat (limited to 'drivers/marvell/ap807_clocks_init.c')
| -rw-r--r-- | drivers/marvell/ap807_clocks_init.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/marvell/ap807_clocks_init.c b/drivers/marvell/ap807_clocks_init.c index 04c256b61..5604453bb 100644 --- a/drivers/marvell/ap807_clocks_init.c +++ b/drivers/marvell/ap807_clocks_init.c @@ -96,6 +96,11 @@ void ap807_clocks_init(unsigned int freq_option) case CPU_2000_DDR_1200_RCLK_1200: pll_set_freq(PLL_FREQ_2000); break; +#ifdef MVEBU_SOC_AP807 + case CPU_2200_DDR_1200_RCLK_1200: + pll_set_freq(PLL_FREQ_2200); + break; +#endif default: break; } |