diff options
| author | Yann Gautier <yann.gautier@st.com> | 2019-06-04 15:55:37 +0200 |
|---|---|---|
| committer | Yann Gautier <yann.gautier@st.com> | 2019-06-17 14:03:51 +0200 |
| commit | dd98aec87ca83054c9bc7502d018e46b02536eb1 (patch) | |
| tree | 64a6e0de66ab7c1ba538dd25fbdbbc1ae5a17983 /drivers/st | |
| parent | d4151d2ff99cba5a1703b647f84db8882a05eab7 (diff) | |
| download | arm-trusted-firmware-dd98aec87ca83054c9bc7502d018e46b02536eb1.tar.gz | |
clk: stm32mp1: correctly handle Clock Spreading Generator
To activate the CSG option, the driver needs to set the bit2
of PLLNCR register = SSCG_CTRL: Spread Spectrum Clock Generator.
This bit should not be cleared when starting the PLL.
Change-Id: Ie5c720ff03655f27a7e7e9e7ccf8295dd046112f
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Diffstat (limited to 'drivers/st')
| -rw-r--r-- | drivers/st/clk/stm32mp1_clk.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c index 855e98b42..cea1c46f3 100644 --- a/drivers/st/clk/stm32mp1_clk.c +++ b/drivers/st/clk/stm32mp1_clk.c @@ -1313,7 +1313,11 @@ static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; - mmio_write_32(pllxcr, RCC_PLLNCR_PLLON); + /* Preserve RCC_PLLNCR_SSCG_CTRL value */ + mmio_clrsetbits_32(pllxcr, + RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | + RCC_PLLNCR_DIVREN, + RCC_PLLNCR_PLLON); } static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) @@ -1442,6 +1446,9 @@ static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) RCC_PLLNCSGR_SSCG_MODE_MASK; mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); + + mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr, + RCC_PLLNCR_SSCG_CTRL); } static int stm32mp1_set_clksrc(unsigned int clksrc) |