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| author | Avinash Mehta <avinash.mehta@arm.com> | 2019-12-18 10:13:40 +0000 |
|---|---|---|
| committer | Avinash Mehta <avinash.mehta@arm.com> | 2020-01-07 14:41:49 +0000 |
| commit | 786890caaeb3e3d01a3a5986a4e4af104c510e62 (patch) | |
| tree | 4b768c276fe22ac60cf5bf7c279d1c588b842fe7 /fdts | |
| parent | 86ed8953b5233570c49a58060d424b7863d3a396 (diff) | |
| download | arm-trusted-firmware-786890caaeb3e3d01a3a5986a4e4af104c510e62.tar.gz | |
A5DS: Correct system freq, Cache Writeback Granule
Correct the system, timer and uart frequencies to successfully run
the stack on FPGA
Correct Cortex-A5MPcore to 8 word granularity for Cache writeback
Change-Id: I2c59c26b7dca440791ad39f2297c68ae513da7b6
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>
Diffstat (limited to 'fdts')
| -rw-r--r-- | fdts/a5ds.dts | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/fdts/a5ds.dts b/fdts/a5ds.dts index fc8783dd8..31d635ac8 100644 --- a/fdts/a5ds.dts +++ b/fdts/a5ds.dts @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -64,10 +64,17 @@ arm,tag-latency = <1 1 1>; }; - refclk100mhz: refclk100mhz { + refclk7500khz: refclk7500khz { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <100000000>; + clock-frequency = <7500000>; + clock-output-names = "apb_pclk"; + }; + + refclk24mhz: refclk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; clock-output-names = "apb_pclk"; }; @@ -82,7 +89,7 @@ rtc@1a220000 { compatible = "arm,pl031", "arm,primecell"; reg = <0x1a220000 0x1000>; - clocks = <&refclk100mhz>; + clocks = <&refclk24mhz>; interrupts = <0 6 0xf04>; clock-names = "apb_pclk"; }; @@ -102,7 +109,7 @@ reg = <0x1a200000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 8 0xf04>; - clocks = <&refclk100mhz>; + clocks = <&refclk7500khz>; clock-names = "apb_pclk"; }; @@ -111,7 +118,7 @@ reg = <0x1a210000 0x1000>; interrupt-parent = <&gic>; interrupts = <0 9 0xf04>; - clocks = <&refclk100mhz>; + clocks = <&refclk7500khz>; clock-names = "apb_pclk"; }; |