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| author | Vishnu Banavath <vishnu.banavath@arm.com> | 2019-12-13 16:53:17 +0000 |
|---|---|---|
| committer | vishnu.banavath <vishnu.banavath@arm.com> | 2019-12-18 16:40:49 +0000 |
| commit | 79c6c342e0abb1de2306ca51fc72794143413a07 (patch) | |
| tree | 50f4d323101e54e595dd56bff164a73413b27695 /fdts | |
| parent | 31645dde0b9fb189fe69f8630ec10630b00c488d (diff) | |
| download | arm-trusted-firmware-79c6c342e0abb1de2306ca51fc72794143413a07.tar.gz | |
fdts: a5ds: add L2 cache node in devicetree
This change is to add L2 cache node into a5ds device tree.
Change-Id: I64b4b3e839c3ee565abbcd1567d1aa358c32d947
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
Diffstat (limited to 'fdts')
| -rw-r--r-- | fdts/a5ds.dts | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/fdts/a5ds.dts b/fdts/a5ds.dts index 91212e8a0..042b6afc5 100644 --- a/fdts/a5ds.dts +++ b/fdts/a5ds.dts @@ -27,24 +27,28 @@ compatible = "arm,cortex-a5"; enable-method = "psci"; reg = <0>; + next-level-cache = <&L2>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a5"; enable-method = "psci"; reg = <1>; + next-level-cache = <&L2>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a5"; enable-method = "psci"; reg = <2>; + next-level-cache = <&L2>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a5"; enable-method = "psci"; reg = <3>; + next-level-cache = <&L2>; }; }; @@ -53,6 +57,16 @@ reg = <0x80000000 0x7F000000>; }; + L2: cache-controller@1C010000 { + compatible = "arm,pl310-cache"; + reg = <0x1C010000 0x1000>; + interrupts = <0 84 4>; + cache-level = <2>; + cache-unified; + arm,data-latency = <1 1 1>; + arm,tag-latency = <1 1 1>; + }; + refclk100mhz: refclk100mhz { compatible = "fixed-clock"; #clock-cells = <0>; |