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authorAndroid Build Coastguard Worker <android-build-coastguard-worker@google.com>2022-05-10 06:55:54 +0000
committerAndroid Build Coastguard Worker <android-build-coastguard-worker@google.com>2022-05-10 06:55:54 +0000
commitc537c0163739dbe6560e22be0b8a13c683a71292 (patch)
tree48f7e7e1c9d2b0913361c2f1a922b3a36b97aa0b /include/drivers/arm/tzc400.h
parent745b077357e2e9aa5f3b67c0f3453fd4241293ee (diff)
parentd2ebd507612c6d0e62ab68cc89a76b29d47a4394 (diff)
downloadarm-trusted-firmware-c537c0163739dbe6560e22be0b8a13c683a71292.tar.gz
Snap for 8564071 from d2ebd507612c6d0e62ab68cc89a76b29d47a4394 to mainline-extservices-releaseaml_ext_331814220aml_ext_331412000aml_ext_331312000aml_ext_331112010aml_ext_331012020android13-mainline-extservices-release
Change-Id: Ic8ba24c3d966a7e5e636dfa8866bacdc729ad48f
Diffstat (limited to 'include/drivers/arm/tzc400.h')
-rw-r--r--include/drivers/arm/tzc400.h16
1 files changed, 8 insertions, 8 deletions
diff --git a/include/drivers/arm/tzc400.h b/include/drivers/arm/tzc400.h
index 32aeb0350..5f8a48f57 100644
--- a/include/drivers/arm/tzc400.h
+++ b/include/drivers/arm/tzc400.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -65,8 +65,8 @@
#define FAIL_CONTROL_NS_SECURE U(0)
#define FAIL_CONTROL_NS_NONSECURE U(1)
#define FAIL_CONTROL_PRIV_SHIFT 20
-#define FAIL_CONTROL_PRIV_PRIV U(0)
-#define FAIL_CONTROL_PRIV_UNPRIV U(1)
+#define FAIL_CONTROL_PRIV_UNPRIV U(0)
+#define FAIL_CONTROL_PRIV_PRIV U(1)
/*
* FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific.
@@ -80,11 +80,8 @@
/* Filter enable bits in a TZC */
#define TZC_400_REGION_ATTR_F_EN_MASK U(0xf)
-#define TZC_400_REGION_ATTR_FILTER_BIT(x) \
- ((U(1) << (x)) << TZC_REGION_ATTR_F_EN_SHIFT)
-#define TZC_400_REGION_ATTR_FILTER_BIT_ALL \
- (TZC_400_REGION_ATTR_F_EN_MASK << \
- TZC_REGION_ATTR_F_EN_SHIFT)
+#define TZC_400_REGION_ATTR_FILTER_BIT(x) (U(1) << (x))
+#define TZC_400_REGION_ATTR_FILTER_BIT_ALL TZC_400_REGION_ATTR_F_EN_MASK
/*
* All TZC region configuration registers are placed one after another. It
@@ -93,6 +90,8 @@
#define TZC_400_REGION_SIZE U(0x20)
#define TZC_400_ACTION_OFF U(0x4)
+#define FILTER_OFFSET U(0x10)
+
#ifndef __ASSEMBLER__
#include <cdefs.h>
@@ -113,6 +112,7 @@ void tzc400_configure_region(unsigned int filters,
void tzc400_set_action(unsigned int action);
void tzc400_enable_filters(void);
void tzc400_disable_filters(void);
+int tzc400_it_handler(void);
static inline void tzc_init(uintptr_t base)
{