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| author | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2018-08-02 10:14:12 +0100 |
|---|---|---|
| committer | Jeenu Viswambharan <jeenu.viswambharan@arm.com> | 2018-08-20 09:05:39 +0100 |
| commit | 30a8d96e4689be30b2caeb23fd071fadd1ec87cd (patch) | |
| tree | cff3a2039870c9ed7a113dd89fe77d185e0e83d1 /include/lib/extensions/ras_arch.h | |
| parent | 03b645ed866a46a8762dfff20acc0bd35a54e34f (diff) | |
| download | arm-trusted-firmware-30a8d96e4689be30b2caeb23fd071fadd1ec87cd.tar.gz | |
RAS: MISRA fixes
These changes address most of the required MISRA rules. In the process,
some from generic code is also fixed.
No functional changes.
Change-Id: I76cacf6e1d73b09510561b5090c2bb66d81bec88
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
Diffstat (limited to 'include/lib/extensions/ras_arch.h')
| -rw-r--r-- | include/lib/extensions/ras_arch.h | 23 |
1 files changed, 12 insertions, 11 deletions
diff --git a/include/lib/extensions/ras_arch.h b/include/lib/extensions/ras_arch.h index 6ec4da80f..e6cd736ae 100644 --- a/include/lib/extensions/ras_arch.h +++ b/include/lib/extensions/ras_arch.h @@ -11,28 +11,28 @@ * Size of nodes implementing Standard Error Records - currently only 4k is * supported. */ -#define STD_ERR_NODE_SIZE_NUM_K 4 +#define STD_ERR_NODE_SIZE_NUM_K 4U /* * Individual register offsets within an error record in Standard Error Record * format when error records are accessed through memory-mapped registers. */ -#define ERR_FR(n) (0x0 + (64 * (n))) -#define ERR_CTLR(n) (0x8 + (64 * (n))) -#define ERR_STATUS(n) (0x10 + (64 * (n))) -#define ERR_ADDR(n) (0x18 + (64 * (n))) -#define ERR_MISC0(n) (0x20 + (64 * (n))) -#define ERR_MISC1(n) (0x28 + (64 * (n))) +#define ERR_FR(n) (0x0ULL + (64ULL * (n))) +#define ERR_CTLR(n) (0x8ULL + (64ULL * (n))) +#define ERR_STATUS(n) (0x10ULL + (64ULL * (n))) +#define ERR_ADDR(n) (0x18ULL + (64ULL * (n))) +#define ERR_MISC0(n) (0x20ULL + (64ULL * (n))) +#define ERR_MISC1(n) (0x28ULL + (64ULL * (n))) /* Group Status Register (ERR_STATUS) offset */ #define ERR_GSR(base, size_num_k, n) \ - ((base) + (0x380 * (size_num_k)) + (8 * (n))) + ((base) + (0x380ULL * (size_num_k)) + (8ULL * (n))) /* Management register offsets */ #define ERR_DEVID(base, size_num_k) \ - ((base) + ((0x400 * (size_num_k)) - 0x100) + 0xc8) + ((base) + ((0x400ULL * (size_num_k)) - 0x100ULL) + 0xc8ULL) -#define ERR_DEVID_MASK 0xffff +#define ERR_DEVID_MASK 0xffffUL /* Standard Error Record status register fields */ #define ERR_STATUS_AV_SHIFT 31 @@ -244,7 +244,8 @@ static inline uint64_t ser_get_misc1(uintptr_t base, unsigned int idx) */ static inline void ser_sys_select_record(unsigned int idx) { - unsigned int max_idx __unused = read_erridr_el1() & ERRIDR_MASK; + unsigned int max_idx __unused = + (unsigned int) read_erridr_el1() & ERRIDR_MASK; assert(idx < max_idx); |