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| author | johpow01 <john.powell@arm.com> | 2020-10-06 17:55:25 -0500 |
|---|---|---|
| committer | John_Powell <john.powell@arm.com> | 2021-01-12 18:06:37 +0000 |
| commit | e26c59d2c968eb0122bf1c333d5ceba534d5fe45 (patch) | |
| tree | 9d5c4b8666dbabf4581bd4d378e4b44cb77ad197 /include/lib | |
| parent | 6e886a475734310f5079945be442490d146e0c04 (diff) | |
| download | arm-trusted-firmware-e26c59d2c968eb0122bf1c333d5ceba534d5fe45.tar.gz | |
Workaround for Cortex A78 erratum 1941498
Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions
r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1
register, there is a small performance cost (<0.5%) for setting this bit.
SDEN can be found here:
https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a78.h | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h index 0d4712b6a..caa512046 100644 --- a/include/lib/cpus/aarch64/cortex_a78.h +++ b/include/lib/cpus/aarch64/cortex_a78.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * Copyright (c) 2019-2021, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,17 +15,18 @@ * CPU Extended Control register specific definitions. ******************************************************************************/ #define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) /******************************************************************************* * CPU Power Control register specific definitions ******************************************************************************/ -#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A78_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) /******************************************************************************* * CPU Auxiliary Control register specific definitions. ******************************************************************************/ -#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30) +#define CORTEX_A78_ACTLR_TAM_BIT (ULL(1) << 30) #define CORTEX_A78_ACTLR2_EL1 S3_0_C15_C1_1 #define CORTEX_A78_ACTLR2_EL1_BIT_1 (ULL(1) << 1) @@ -33,12 +34,12 @@ /******************************************************************************* * CPU Activity Monitor Unit register specific definitions. ******************************************************************************/ -#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4 -#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5 -#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0 -#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1 +#define CPUAMCNTENCLR0_EL0 S3_3_C15_C2_4 +#define CPUAMCNTENSET0_EL0 S3_3_C15_C2_5 +#define CPUAMCNTENCLR1_EL0 S3_3_C15_C3_0 +#define CPUAMCNTENSET1_EL0 S3_3_C15_C3_1 -#define CORTEX_A78_AMU_GROUP0_MASK U(0xF) -#define CORTEX_A78_AMU_GROUP1_MASK U(0x7) +#define CORTEX_A78_AMU_GROUP0_MASK U(0xF) +#define CORTEX_A78_AMU_GROUP1_MASK U(0x7) #endif /* CORTEX_A78_H */ |