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| author | nayanpatel-arm <nayankumar.patel@arm.com> | 2021-09-28 17:31:50 -0700 |
|---|---|---|
| committer | nayankumar.patel <nayankumar.patel@arm.com> | 2021-10-01 21:21:07 +0200 |
| commit | b36fe21243d2113cb3dbd746a3698cd112948fa3 (patch) | |
| tree | 3403ed1317fe8d6e979102efd6b77a15f033a9fb /include/lib | |
| parent | 8e140272fbd4ea00d1a9d86dced18ce6eb3a9981 (diff) | |
| download | arm-trusted-firmware-b36fe21243d2113cb3dbd746a3698cd112948fa3.tar.gz | |
errata: workaround for Cortex-A78 erratum 2132060
Cortex-A78 erratum 2132060 is a Cat B erratum that applies to
revisions r0p0, r1p0, r1p1, and r1p2 of CPU. It is still open.
The workaround is to write the value 2'b11 to the PF_MODE bits
in the CPUECTLR_EL1 register which will place the data prefetcher
in the most conservative mode instead of disabling it.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1401784/latest
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: If7dec72578633d37d110d103099e406c3a970ff7
Diffstat (limited to 'include/lib')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a78.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h index 4bc49f303..42b08336d 100644 --- a/include/lib/cpus/aarch64/cortex_a78.h +++ b/include/lib/cpus/aarch64/cortex_a78.h @@ -16,6 +16,9 @@ ******************************************************************************/ #define CORTEX_A78_CPUECTLR_EL1 S3_0_C15_C1_4 #define CORTEX_A78_CPUECTLR_EL1_BIT_8 (ULL(1) << 8) +#define CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3) +#define CPUECTLR_EL1_PF_MODE_LSB U(6) +#define CPUECTLR_EL1_PF_MODE_WIDTH U(2) /******************************************************************************* * CPU Power Control register specific definitions |