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authorVarun Wadekar <vwadekar@nvidia.com>2021-08-26 12:18:59 +0200
committerTrustedFirmware Code Review <review@review.trustedfirmware.org>2021-08-26 12:18:59 +0200
commitd0464435f6ba4e8eca6f38bebd3f0a00b9a1b378 (patch)
tree110a79e585276469f3e5c0bbdef2445f9a4e8434 /include/lib
parentabd63ed0c575a2517c43fe8dc4321d6e9fc512c3 (diff)
parent47d6f5ff16d1f2ad009d630a381054b10fa0a06f (diff)
downloadarm-trusted-firmware-d0464435f6ba4e8eca6f38bebd3f0a00b9a1b378.tar.gz
Merge "feat(cpus): workaround for Cortex A78 AE erratum 1941500" into integration
Diffstat (limited to 'include/lib')
-rw-r--r--include/lib/cpus/aarch64/cortex_a78_ae.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a78_ae.h b/include/lib/cpus/aarch64/cortex_a78_ae.h
index 24ae7eeac..0c8adcf1b 100644
--- a/include/lib/cpus/aarch64/cortex_a78_ae.h
+++ b/include/lib/cpus/aarch64/cortex_a78_ae.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2020, ARM Limited. All rights reserved.
+ * Copyright (c) 2021, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,4 +12,10 @@
#define CORTEX_A78_AE_MIDR U(0x410FD420)
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define CORTEX_A78_AE_CPUECTLR_EL1 CORTEX_A78_CPUECTLR_EL1
+#define CORTEX_A78_AE_CPUECTLR_EL1_BIT_8 CORTEX_A78_CPUECTLR_EL1_BIT_8
+
#endif /* CORTEX_A78_AE_H */