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| author | johpow01 <john.powell@arm.com> | 2021-05-03 15:33:39 -0500 |
|---|---|---|
| committer | johpow01 <john.powell@arm.com> | 2021-07-16 15:20:36 -0500 |
| commit | 33e3e925415f36f81b593dc269d203ad2165e13e (patch) | |
| tree | f4f8eb249e3ecb495677870252fea3fa7dfc540a /include | |
| parent | 41e893fff445c0c272303961a38f14cb54f2e8ab (diff) | |
| download | arm-trusted-firmware-33e3e925415f36f81b593dc269d203ad2165e13e.tar.gz | |
errata: workaround for Neoverse V1 errata 1791573
Neoverse V1 erratum 1791573 is a Cat B erratum present in r0p0 and
r1p0 of the V1 processor core. It is fixed in r1p1.
SDEN can be found here:
https://documentation-service.arm.com/static/60d499080320e92fa40b4625
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ic6f92da4d0b995bd04ca5b1673ffeedaebb71d10
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_v1.h | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h index 650eb4d41..cea26599f 100644 --- a/include/lib/cpus/aarch64/neoverse_v1.h +++ b/include/lib/cpus/aarch64/neoverse_v1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * Copyright (c) 2019-2021, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,4 +20,10 @@ #define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +/******************************************************************************* + * CPU Auxiliary Control register specific definitions. + ******************************************************************************/ +#define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1 +#define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2) + #endif /* NEOVERSE_V1_H */ |