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| author | Bipin Ravi <bipin.ravi@arm.com> | 2021-03-31 18:45:55 -0500 |
|---|---|---|
| committer | Bipin Ravi <bipin.ravi@arm.com> | 2021-09-03 15:44:56 -0500 |
| commit | afc2ed63f9c83a3b7408d804cbe22f02d34d075d (patch) | |
| tree | daf947db21682ae911e9b73636ec51ae96e92e0a /include | |
| parent | 213afde907a375f4f28ac1843b633ca83887f174 (diff) | |
| download | arm-trusted-firmware-afc2ed63f9c83a3b7408d804cbe22f02d34d075d.tar.gz | |
errata: workaround for Cortex-A710 erratum 2017096
Cortex-A710 erratum 2017096 is a Cat B erratum that applies to
revisions r0p0, r1p0 & r2p0 and is still open. The workaround is to
set CPUECLTR_EL1[8] to 1 which disables store issue prefetching.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775101/latest
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Change-Id: If5f61ec30dbc2fab7f2c68663996057086e374e3
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a710.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/cortex_a710.h b/include/lib/cpus/aarch64/cortex_a710.h index 5c81de837..8b011aaea 100644 --- a/include/lib/cpus/aarch64/cortex_a710.h +++ b/include/lib/cpus/aarch64/cortex_a710.h @@ -13,6 +13,7 @@ * CPU Extended Control register specific definitions ******************************************************************************/ #define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4 +#define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) /******************************************************************************* * CPU Power Control register specific definitions |