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| author | johpow01 <john.powell@arm.com> | 2020-06-02 13:14:11 -0500 |
|---|---|---|
| committer | John Powell <john.powell@arm.com> | 2020-06-25 19:58:35 +0000 |
| commit | 0e0521bdfce73be7dbded23e560b3dab1ff1af2d (patch) | |
| tree | cd1fba5d1538fae0b9d808bd9244d7d9e661fc44 /include | |
| parent | 24cdbb22a9da2eb7d07592774777012552a5dd41 (diff) | |
| download | arm-trusted-firmware-0e0521bdfce73be7dbded23e560b3dab1ff1af2d.tar.gz | |
Workaround for Neoverse N1 erratum 1800710
Neoverse N1 erratum 1800710 is a Cat B erratum, present in older
revisions of the Neoverse N1 processor core. The workaround is to
set a bit in the ECTLR_EL1 system register, which disables allocation
of splintered pages in the L2 TLB.
This errata is explained in this SDEN:
https://static.docs.arm.com/sden885747/f/Arm_Neoverse_N1_MP050_Software_Developer_Errata_Notice_v21.pdf
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ie5b15c8bc3235e474a06a57c3ec70684361857a6
Diffstat (limited to 'include')
| -rw-r--r-- | include/lib/cpus/aarch64/neoverse_n1.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/lib/cpus/aarch64/neoverse_n1.h b/include/lib/cpus/aarch64/neoverse_n1.h index b50befa8d..155a90e0d 100644 --- a/include/lib/cpus/aarch64/neoverse_n1.h +++ b/include/lib/cpus/aarch64/neoverse_n1.h @@ -35,6 +35,7 @@ #define NEOVERSE_N1_WS_THR_L2_MASK (ULL(3) << 24) #define NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT (ULL(1) << 51) +#define NEOVERSE_N1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53) #define NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT (ULL(1) << 0) /******************************************************************************* |