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| author | Madhukar Pappireddy <madhukar.pappireddy@arm.com> | 2021-11-08 15:28:19 +0100 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2021-11-08 15:28:19 +0100 |
| commit | 0b5e33c7aa6cf5723f68a2b6170b155832c965d1 (patch) | |
| tree | efcbed23ee8532247732888c15bb6bc7f1d7732b /lib/cpus/aarch64/cortex_a78.S | |
| parent | 683bb4d7bdfd42e6e026902c43797f132b2a75d5 (diff) | |
| parent | 4c8fe6b17fa994a630b2a30f8666df103f2e370d (diff) | |
| download | arm-trusted-firmware-0b5e33c7aa6cf5723f68a2b6170b155832c965d1.tar.gz | |
Merge changes Ic2f90d79,Ieca02425,I615bcc1f,I6a9cb4a2,I5247f8f8, ... into integration
* changes:
fix(errata): workaround for Neoverse V1 erratum 2216392
fix(errata): workaround for Cortex A78 erratum 2242635
fix(errata): workaround for Neoverse-N2 erratum 2280757
fix(errata): workaround for Neoverse-N2 erratum 2242400
fix(errata): workaround for Neoverse-N2 erratum 2138958
fix(errata): workaround for Neoverse-N2 erratum 2242415
Diffstat (limited to 'lib/cpus/aarch64/cortex_a78.S')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a78.S | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S index 4e8a228ed..a1288bab1 100644 --- a/lib/cpus/aarch64/cortex_a78.S +++ b/lib/cpus/aarch64/cortex_a78.S @@ -227,6 +227,42 @@ func check_errata_2132060 b cpu_rev_var_ls endfunc check_errata_2132060 +/* -------------------------------------------------------------------- + * Errata Workaround for A78 Erratum 2242635. + * This applies to revisions r1p0, r1p1, and r1p2 of the Cortex A78 + * processor and is still open. + * The issue also exists in r0p0 but there is no fix in that revision. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------------------------- + */ +func errata_a78_2242635_wa + /* Compare x0 against revisions r1p0 - r1p2 */ + mov x17, x30 + bl check_errata_2242635 + cbz x0, 1f + + ldr x0, =0x5 + msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ + ldr x0, =0x10F600E000 + msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ + ldr x0, =0x10FF80E000 + msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ + ldr x0, =0x80000000003FF + msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ + + isb +1: + ret x17 +endfunc errata_a78_2242635_wa + +func check_errata_2242635 + /* Applies to revisions r1p0 through r1p2. */ + mov x1, #CPU_REV(1, 0) + mov x2, #CPU_REV(1, 2) + b cpu_rev_var_range +endfunc check_errata_2242635 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A78 * ------------------------------------------------- @@ -266,6 +302,11 @@ func cortex_a78_reset_func bl errata_a78_2132060_wa #endif +#if ERRATA_A78_2242635 + mov x0, x18 + bl errata_a78_2242635_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 @@ -326,6 +367,7 @@ func cortex_a78_errata_report report_errata ERRATA_A78_1821534, cortex_a78, 1821534 report_errata ERRATA_A78_1952683, cortex_a78, 1952683 report_errata ERRATA_A78_2132060, cortex_a78, 2132060 + report_errata ERRATA_A78_2242635, cortex_a78, 2242635 ldp x8, x30, [sp], #16 ret |