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author | Android Build Coastguard Worker <android-build-coastguard-worker@google.com> | 2023-07-07 04:59:52 +0000 |
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committer | Android Build Coastguard Worker <android-build-coastguard-worker@google.com> | 2023-07-07 04:59:52 +0000 |
commit | 2beb3a69f30a600ae3ec27334e189649379b9329 (patch) | |
tree | 2ce8a4e341ac9f98fb265347777487eda74eba48 /lib/cpus/aarch64/cortex_hunter.S | |
parent | 0f2974e30f5150b29f1dff5ec041d74ac687327c (diff) | |
parent | 138668cae2394deb5d695c70fe4aa9760c4458ee (diff) | |
download | arm-trusted-firmware-2beb3a69f30a600ae3ec27334e189649379b9329.tar.gz |
Snap for 10453563 from 138668cae2394deb5d695c70fe4aa9760c4458ee to mainline-os-statsd-releaseaml_sta_341710000aml_sta_341615000aml_sta_341511040aml_sta_341410000aml_sta_341311010aml_sta_341114000aml_sta_341111000aml_sta_341010020aml_sta_340912000aml_sta_340911000aml_net_341111030android14-mainline-os-statsd-release
Change-Id: I4cf7f6eba068f9a96359b9ea4386cfb69e72d1ea
Diffstat (limited to 'lib/cpus/aarch64/cortex_hunter.S')
-rw-r--r-- | lib/cpus/aarch64/cortex_hunter.S | 77 |
1 files changed, 77 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/cortex_hunter.S b/lib/cpus/aarch64/cortex_hunter.S new file mode 100644 index 000000000..2ab429615 --- /dev/null +++ b/lib/cpus/aarch64/cortex_hunter.S @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <common/bl_common.h> +#include <cortex_hunter.h> +#include <cpu_macros.S> +#include <plat_macros.S> + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex Hunter must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex Hunter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + +func cortex_hunter_reset_func + /* Disable speculative loads */ + msr SSBS, xzr + isb + ret +endfunc cortex_hunter_reset_func + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_hunter_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + mrs x0, CORTEX_HUNTER_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_HUNTER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_HUNTER_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_hunter_core_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Cortex Hunter. Must follow AAPCS. + */ +func cortex_hunter_errata_report + ret +endfunc cortex_hunter_errata_report +#endif + + /* --------------------------------------------- + * This function provides Cortex Hunter-specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_hunter_regs, "aS" +cortex_hunter_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_hunter_cpu_reg_dump + adr x6, cortex_hunter_regs + mrs x8, CORTEX_HUNTER_CPUECTLR_EL1 + ret +endfunc cortex_hunter_cpu_reg_dump + +declare_cpu_ops cortex_hunter, CORTEX_HUNTER_MIDR, \ + cortex_hunter_reset_func, \ + cortex_hunter_core_pwr_dwn |