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authorOlivier Deprez <olivier.deprez@arm.com>2021-05-25 12:06:03 +0200
committerOlivier Deprez <olivier.deprez@arm.com>2021-06-03 09:31:10 +0200
commit2e61d6871cc310e9404fe5cfa10b9828f1c869a7 (patch)
tree61024a28709256c620be75b3811bdeb3fa84af40 /lib/cpus
parent203d48adcad8d90eb8fb5eb4bb2de4c65c9837af (diff)
downloadarm-trusted-firmware-2e61d6871cc310e9404fe5cfa10b9828f1c869a7.tar.gz
fix: random typos in tf-a code base
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Id610f7e4398e799a2fbd74861274fd684c32db53
Diffstat (limited to 'lib/cpus')
-rw-r--r--lib/cpus/aarch64/cpu_helpers.S4
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S
index 730b09beb..bd8f85f6d 100644
--- a/lib/cpus/aarch64/cpu_helpers.S
+++ b/lib/cpus/aarch64/cpu_helpers.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2021, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -144,7 +144,7 @@ endfunc do_cpu_reg_dump
* If cpu_ops for the MIDR_EL1 cannot be found and
* SUPPORT_UNKNOWN_MPID is enabled, it will try to look for a
* default cpu_ops with an MIDR value of 0.
- * (Implementation number 0x0 should be reseverd for software use
+ * (Implementation number 0x0 should be reserved for software use
* and therefore no clashes should happen with that default value).
*
* Return :