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| author | nayanpatel-arm <nayankumar.patel@arm.com> | 2021-08-25 17:35:15 -0700 |
|---|---|---|
| committer | nayanpatel-arm <nayankumar.patel@arm.com> | 2021-08-25 17:35:15 -0700 |
| commit | a64bcc2b4528962a3b11ac3798e36e52dca2787f (patch) | |
| tree | 9debc5e1989d9c3d571b1e59cfd408cb37f260b5 /lib/cpus | |
| parent | fbcf54aeb970195ea2944cb7bbc704145ec8f07e (diff) | |
| download | arm-trusted-firmware-a64bcc2b4528962a3b11ac3798e36e52dca2787f.tar.gz | |
errata: workaround for Cortex-A710 errata 2081180
Cortex-A710 erratum 2081180 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.
A710 SDEN: https://developer.arm.com/documentation/SDEN1775101/1000
Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I1e8c2bc3d8dc326947ccfd91daf9083d666b2542
Diffstat (limited to 'lib/cpus')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a710.S | 49 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 8 |
2 files changed, 57 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index 39700350d..469b430a9 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -64,6 +64,49 @@ func check_errata_1987031 b cpu_rev_var_ls endfunc check_errata_1987031 +/* -------------------------------------------------- + * Errata Workaround for Cortex-A710 Erratum 2081180. + * This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710. + * It is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a710_2081180_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2081180 + cbz x0, 1f + + /* Apply instruction patching sequence */ + ldr x0,=0x3 + msr S3_6_c15_c8_0,x0 + ldr x0,=0xF3A08002 + msr S3_6_c15_c8_2,x0 + ldr x0,=0xFFF0F7FE + msr S3_6_c15_c8_3,x0 + ldr x0,=0x10002001003FF + msr S3_6_c15_c8_1,x0 + ldr x0,=0x4 + msr S3_6_c15_c8_0,x0 + ldr x0,=0xBF200000 + msr S3_6_c15_c8_2,x0 + ldr x0,=0xFFEF0000 + msr S3_6_c15_c8_3,x0 + ldr x0,=0x10002001003F3 + msr S3_6_c15_c8_1,x0 + isb +1: + ret x17 +endfunc errata_a710_2081180_wa + +func check_errata_2081180 + /* Applies to r0p0, r1p0 and r2p0 */ + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_2081180 + /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- @@ -95,6 +138,7 @@ func cortex_a710_errata_report * checking functions of each errata. */ report_errata ERRATA_A710_1987031, cortex_a710, 1987031 + report_errata ERRATA_A710_2081180, cortex_a710, 2081180 ldp x8, x30, [sp], #16 ret @@ -115,6 +159,11 @@ func cortex_a710_reset_func bl errata_a710_1987031_wa #endif +#if ERRATA_A710_2081180 + mov x0, x18 + bl errata_a710_2081180_wa +#endif + isb ret x19 endfunc cortex_a710_reset_func diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index ed507c856..83d31f996 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -409,6 +409,10 @@ ERRATA_V1_2139242 ?=0 # to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. ERRATA_A710_1987031 ?=0 +# Flag to apply erratum 2081180 workaround during reset. This erratum applies +# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. +ERRATA_A710_2081180 ?=0 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. ERRATA_DSU_798953 ?=0 @@ -750,6 +754,10 @@ $(eval $(call add_define,ERRATA_V1_2139242)) $(eval $(call assert_boolean,ERRATA_A710_1987031)) $(eval $(call add_define,ERRATA_A710_1987031)) +# Process ERRATA_A710_2081180 flag +$(eval $(call assert_boolean,ERRATA_A710_2081180)) +$(eval $(call add_define,ERRATA_A710_2081180)) + # Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953)) |