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| author | Varun Wadekar <vwadekar@nvidia.com> | 2018-02-27 18:30:31 -0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2018-09-04 17:33:32 -0700 |
| commit | 1593cae46e03eda613d50a0e1702729fbef9f79e (patch) | |
| tree | 7a5bdc07d56136f7a8de1674482afb779c821344 /lib/cpus | |
| parent | 1916092ffb4abf2e63afe4e59df2c6ee4c4b8d4d (diff) | |
| download | arm-trusted-firmware-1593cae46e03eda613d50a0e1702729fbef9f79e.tar.gz | |
denver: use plat_my_core_pos() to get core position
The current functions to disable and enable Dynamic Code Optimizer
(DCO) assume that all denver cores are in the same cluster. They
ignore AFF1 field of the mpidr_el1 register, which leads to
incorect logical core id calculation.
This patch calls the platform handler, plat_my_core_pos(), to get
the logical core id to disable/enable DCO for the core.
Original change by: Krishna Sitaraman <ksitaraman@nvidia.com>
Change-Id: I45fbd1f1eb032cc1db677a4fdecc554548b4a830
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'lib/cpus')
| -rw-r--r-- | lib/cpus/aarch64/denver.S | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S index a981d02c7..caf74d7b9 100644 --- a/lib/cpus/aarch64/denver.S +++ b/lib/cpus/aarch64/denver.S @@ -156,11 +156,12 @@ endfunc denver_disable_ext_debug * ---------------------------------------------------- */ func denver_enable_dco - mrs x0, mpidr_el1 - and x0, x0, #0xF + mov x3, x30 + bl plat_my_core_pos mov x1, #1 lsl x1, x1, x0 msr s3_0_c15_c0_2, x1 + mov x30, x3 ret endfunc denver_enable_dco @@ -170,9 +171,10 @@ endfunc denver_enable_dco */ func denver_disable_dco + mov x3, x30 + /* turn off background work */ - mrs x0, mpidr_el1 - and x0, x0, #0xF + bl plat_my_core_pos mov x1, #1 lsl x1, x1, x0 lsl x2, x1, #16 @@ -186,6 +188,7 @@ func denver_disable_dco and x2, x2, x1 cbnz x2, 1b + mov x30, x3 ret endfunc denver_disable_dco |