diff options
| author | Andrew F. Davis <afd@ti.com> | 2018-10-12 15:37:04 -0500 |
|---|---|---|
| committer | Andrew F. Davis <afd@ti.com> | 2018-10-16 09:27:53 -0500 |
| commit | 6a655a85c09a6a1707b40993d261fbafc1f511c5 (patch) | |
| tree | bce49023409f39f2632205a722058b5fdd3e9756 /lib/cpus | |
| parent | 0a09313ec780d2f66efcda3eb2a5d1632719bd81 (diff) | |
| download | arm-trusted-firmware-6a655a85c09a6a1707b40993d261fbafc1f511c5.tar.gz | |
ti: k3: common: Do not disable cache on TI K3 core powerdown
Leave the caches on and explicitly flush any data that
may be stale when the core is powered down. This prevents
non-coherent interconnect access which has negative side-
effects on AM65x.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Diffstat (limited to 'lib/cpus')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a53.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/cortex_a53.S b/lib/cpus/aarch64/cortex_a53.S index 3a23e025f..108509f1f 100644 --- a/lib/cpus/aarch64/cortex_a53.S +++ b/lib/cpus/aarch64/cortex_a53.S @@ -228,11 +228,13 @@ endfunc cortex_a53_reset_func func cortex_a53_core_pwr_dwn mov x18, x30 +#if !TI_AM65X_WORKAROUND /* --------------------------------------------- * Turn off caches. * --------------------------------------------- */ bl cortex_a53_disable_dcache +#endif /* --------------------------------------------- * Flush L1 caches. @@ -252,11 +254,13 @@ endfunc cortex_a53_core_pwr_dwn func cortex_a53_cluster_pwr_dwn mov x18, x30 +#if !TI_AM65X_WORKAROUND /* --------------------------------------------- * Turn off caches. * --------------------------------------------- */ bl cortex_a53_disable_dcache +#endif /* --------------------------------------------- * Flush L1 caches. |