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| author | Android Build Coastguard Worker <android-build-coastguard-worker@google.com> | 2023-07-07 05:09:52 +0000 |
|---|---|---|
| committer | Android Build Coastguard Worker <android-build-coastguard-worker@google.com> | 2023-07-07 05:09:52 +0000 |
| commit | 2acdc134972f4b1faf7e4e86f3425d015dd6f089 (patch) | |
| tree | 2ce8a4e341ac9f98fb265347777487eda74eba48 /lib/xlat_mpu/aarch64/enable_mpu.S | |
| parent | d2ebd507612c6d0e62ab68cc89a76b29d47a4394 (diff) | |
| parent | 138668cae2394deb5d695c70fe4aa9760c4458ee (diff) | |
| download | arm-trusted-firmware-2acdc134972f4b1faf7e4e86f3425d015dd6f089.tar.gz | |
Snap for 10453563 from 138668cae2394deb5d695c70fe4aa9760c4458ee to mainline-uwb-releaseaml_uwb_341710010aml_uwb_341513070aml_uwb_341511050aml_uwb_341310300aml_uwb_341310030aml_uwb_341111010aml_uwb_341011000android14-mainline-uwb-release
Change-Id: I4e93f50d8d89ecf76a67a8412fa96bf8b7247421
Diffstat (limited to 'lib/xlat_mpu/aarch64/enable_mpu.S')
| -rw-r--r-- | lib/xlat_mpu/aarch64/enable_mpu.S | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/lib/xlat_mpu/aarch64/enable_mpu.S b/lib/xlat_mpu/aarch64/enable_mpu.S new file mode 100644 index 000000000..3791f2d9d --- /dev/null +++ b/lib/xlat_mpu/aarch64/enable_mpu.S @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <asm_macros.S> +#include <assert_macros.S> +#include <lib/xlat_tables/xlat_tables_v2.h> +#include <platform_def.h> + + .global enable_mpu_direct_el2 + + /* void enable_mmu_direct_el2(unsigned int flags) */ +func enable_mpu_direct_el2 +#if ENABLE_ASSERTIONS + mrs x1, sctlr_el2 + tst x1, #SCTLR_M_BIT + ASM_ASSERT(eq) +#endif + mov x7, x0 + adrp x0, mmu_cfg_params + add x0, x0, :lo12:mmu_cfg_params + + /* (MAIRs are already set up) */ + + /* TCR */ + ldr x2, [x0, #(MMU_CFG_TCR << 3)] + msr tcr_el2, x2 + + /* + * Ensure all translation table writes have drained into memory, the TLB + * invalidation is complete, and translation register writes are + * committed before enabling the MMU + */ + dsb ish + isb + + /* Set and clear required fields of SCTLR */ + mrs x4, sctlr_el2 + mov_imm x5, SCTLR_WXN_BIT | SCTLR_C_BIT | SCTLR_M_BIT + orr x4, x4, x5 + + /* Additionally, amend SCTLR fields based on flags */ + bic x5, x4, #SCTLR_C_BIT + tst x7, #DISABLE_DCACHE + csel x4, x5, x4, ne + + msr sctlr_el2, x4 + isb + + ret +endfunc enable_mpu_direct_el2 |