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authordavidcunado-arm <david.cunado@arm.com>2017-03-29 17:54:54 +0100
committerGitHub <noreply@github.com>2017-03-29 17:54:54 +0100
commite422f991df48306cd5d9629c4f1ed230b0807fdb (patch)
tree2485d3173aeabcd38eed35928a44c3d680f21715 /lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
parentab139902047d875f70a0a5cd4f35186485bf34ba (diff)
parent5d21b037e16ab8f7c5e63db84a6a9148b7a44a14 (diff)
downloadarm-trusted-firmware-e422f991df48306cd5d9629c4f1ed230b0807fdb.tar.gz
Merge pull request #880 from Summer-ARM/sq/tcr-memory-attribution
Add support to change xlat_tables to non-cacheable
Diffstat (limited to 'lib/xlat_tables_v2/aarch64/xlat_tables_arch.c')
-rw-r--r--lib/xlat_tables_v2/aarch64/xlat_tables_arch.c15
1 files changed, 11 insertions, 4 deletions
diff --git a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
index 235fa4453..575ac71ce 100644
--- a/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
+++ b/lib/xlat_tables_v2/aarch64/xlat_tables_arch.c
@@ -201,11 +201,18 @@ void init_xlat_tables_arch(unsigned long long max_pa)
write_mair_el##_el(mair); \
\
/* Set TCR bits as well. */ \
- /* Inner & outer WBWA & shareable. */ \
/* Set T0SZ to (64 - width of virtual address space) */ \
- tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | \
- TCR_RGN_INNER_WBA | \
- (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
+ if (flags & XLAT_TABLE_NC) { \
+ /* Inner & outer non-cacheable non-shareable. */\
+ tcr = TCR_SH_NON_SHAREABLE | \
+ TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC | \
+ (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
+ } else { \
+ /* Inner & outer WBWA & shareable. */ \
+ tcr = TCR_SH_INNER_SHAREABLE | \
+ TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA | \
+ (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\
+ } \
tcr |= _tcr_extra; \
write_tcr_el##_el(tcr); \
\