Merge changes Ic2f90d79,Ieca02425,I615bcc1f,I6a9cb4a2,I5247f8f8, ... into integration

* changes:
  fix(errata): workaround for Neoverse V1 erratum 2216392
  fix(errata): workaround for Cortex A78 erratum 2242635
  fix(errata): workaround for Neoverse-N2 erratum 2280757
  fix(errata): workaround for Neoverse-N2 erratum 2242400
  fix(errata): workaround for Neoverse-N2 erratum 2138958
  fix(errata): workaround for Neoverse-N2 erratum 2242415

4 files changed, 302 insertions, 22 deletions

diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index 4e8a228ed..a1288bab1 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -227,6 +227,42 @@ func check_errata_2132060
 	b	cpu_rev_var_ls
 endfunc check_errata_2132060
 
+/* --------------------------------------------------------------------
+ * Errata Workaround for A78 Erratum 2242635.
+ * This applies to revisions r1p0, r1p1, and r1p2 of the Cortex A78
+ * processor and is still open.
+ * The issue also exists in r0p0 but there is no fix in that revision.
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x17
+ * --------------------------------------------------------------------
+ */
+func errata_a78_2242635_wa
+	/* Compare x0 against revisions r1p0 - r1p2 */
+	mov	x17, x30
+	bl	check_errata_2242635
+	cbz	x0, 1f
+
+	ldr	x0, =0x5
+	msr	S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
+	ldr	x0, =0x10F600E000
+	msr	S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */
+	ldr	x0, =0x10FF80E000
+	msr	S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
+	ldr	x0, =0x80000000003FF
+	msr	S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */
+
+	isb
+1:
+	ret	x17
+endfunc errata_a78_2242635_wa
+
+func check_errata_2242635
+	/* Applies to revisions r1p0 through r1p2. */
+	mov	x1, #CPU_REV(1, 0)
+	mov	x2, #CPU_REV(1, 2)
+	b	cpu_rev_var_range
+endfunc check_errata_2242635
+
 	/* -------------------------------------------------
 	 * The CPU Ops reset function for Cortex-A78
 	 * -------------------------------------------------
@@ -266,6 +302,11 @@ func cortex_a78_reset_func
 	bl	errata_a78_2132060_wa
 #endif
 
+#if ERRATA_A78_2242635
+	mov	x0, x18
+	bl	errata_a78_2242635_wa
+#endif
+
 #if ENABLE_AMU
 	/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
 	mrs	x0, actlr_el3
@@ -326,6 +367,7 @@ func cortex_a78_errata_report
 	report_errata ERRATA_A78_1821534, cortex_a78, 1821534
 	report_errata ERRATA_A78_1952683, cortex_a78, 1952683
 	report_errata ERRATA_A78_2132060, cortex_a78, 2132060
+	report_errata ERRATA_A78_2242635, cortex_a78, 2242635
 
 	ldp	x8, x30, [sp], #16
 	ret
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
index 330cc596a..621aded7c 100644
--- a/lib/cpus/aarch64/neoverse_n2.S
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -184,6 +184,34 @@ func check_errata_2138956
 endfunc check_errata_2138956
 
 /* --------------------------------------------------
+ * Errata Workaround for Neoverse N2 Erratum 2242415.
+ * This applies to revision r0p0 of Neoverse N2. it is still open.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x1, x17
+ * --------------------------------------------------
+ */
+func errata_n2_2242415_wa
+	/* Check revision. */
+	mov	x17, x30
+	bl	check_errata_2242415
+	cbz	x0, 1f
+
+	/* Apply instruction patching sequence */
+	mrs	x1, NEOVERSE_N2_CPUACTLR_EL1
+	orr	x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
+	msr	NEOVERSE_N2_CPUACTLR_EL1, x1
+1:
+	ret	x17
+endfunc errata_n2_2242415_wa
+
+func check_errata_2242415
+	/* Applies to r0p0 */
+	mov	x1, #0x00
+	b	cpu_rev_var_ls
+endfunc check_errata_2242415
+
+/* --------------------------------------------------
  * Errata Workaround for Neoverse N2 Erratum 2138953.
  * This applies to revision r0p0 of Neoverse N2. it is still open.
  * Inputs:
@@ -212,6 +240,99 @@ func check_errata_2138953
 	b	cpu_rev_var_ls
 endfunc check_errata_2138953
 
+/* --------------------------------------------------
+ * Errata Workaround for Neoverse N2 Erratum 2138958.
+ * This applies to revision r0p0 of Neoverse N2. it is still open.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x1, x17
+ * --------------------------------------------------
+ */
+func errata_n2_2138958_wa
+	/* Check revision. */
+	mov	x17, x30
+	bl	check_errata_2138958
+	cbz	x0, 1f
+
+	/* Apply instruction patching sequence */
+	mrs	x1, NEOVERSE_N2_CPUACTLR5_EL1
+	orr	x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13
+	msr	NEOVERSE_N2_CPUACTLR5_EL1, x1
+1:
+	ret	x17
+endfunc errata_n2_2138958_wa
+
+func check_errata_2138958
+	/* Applies to r0p0 */
+	mov	x1, #0x00
+	b	cpu_rev_var_ls
+endfunc check_errata_2138958
+
+/* --------------------------------------------------
+ * Errata Workaround for Neoverse N2 Erratum 2242400.
+ * This applies to revision r0p0 of Neoverse N2. it is still open.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x1, x17
+ * --------------------------------------------------
+ */
+func errata_n2_2242400_wa
+	/* Check revision. */
+	mov	x17, x30
+	bl	check_errata_2242400
+	cbz	x0, 1f
+
+	/* Apply instruction patching sequence */
+	mrs	x1, NEOVERSE_N2_CPUACTLR5_EL1
+	orr	x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17
+	msr	NEOVERSE_N2_CPUACTLR5_EL1, x1
+	ldr	x0, =0x2
+	msr	S3_6_c15_c8_0, x0
+	ldr	x0, =0x10F600E000
+	msr	S3_6_c15_c8_2, x0
+	ldr	x0, =0x10FF80E000
+	msr	S3_6_c15_c8_3, x0
+	ldr	x0, =0x80000000003FF
+	msr	S3_6_c15_c8_1, x0
+	isb
+1:
+	ret	x17
+endfunc errata_n2_2242400_wa
+
+func check_errata_2242400
+	/* Applies to r0p0 */
+	mov	x1, #0x00
+	b	cpu_rev_var_ls
+endfunc check_errata_2242400
+
+/* --------------------------------------------------
+ * Errata Workaround for Neoverse N2 Erratum 2280757.
+ * This applies to revision r0p0 of Neoverse N2. it is still open.
+ * Inputs:
+ * x0: variant[4:7] and revision[0:3] of current cpu.
+ * Shall clobber: x0-x1, x17
+ * --------------------------------------------------
+ */
+func errata_n2_2280757_wa
+	/* Check revision. */
+	mov	x17, x30
+	bl	check_errata_2280757
+	cbz	x0, 1f
+
+	/* Apply instruction patching sequence */
+	mrs	x1, NEOVERSE_N2_CPUACTLR_EL1
+	orr	x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
+	msr	NEOVERSE_N2_CPUACTLR_EL1, x1
+1:
+	ret	x17
+endfunc errata_n2_2280757_wa
+
+func check_errata_2280757
+	/* Applies to r0p0 */
+	mov	x1, #0x00
+	b	cpu_rev_var_ls
+endfunc check_errata_2280757
+
 	/* -------------------------------------------
 	 * The CPU Ops reset function for Neoverse N2.
 	 * -------------------------------------------
@@ -238,13 +359,13 @@ func neoverse_n2_reset_func
 #endif
 
 #if ERRATA_N2_2025414
-	mov     x0, x18
-	bl      errata_n2_2025414_wa
+	mov	x0, x18
+	bl	errata_n2_2025414_wa
 #endif
 
 #if ERRATA_N2_2189731
-	mov     x0, x18
-	bl      errata_n2_2189731_wa
+	mov	x0, x18
+	bl	errata_n2_2189731_wa
 #endif
 
 
@@ -258,6 +379,26 @@ func neoverse_n2_reset_func
 	bl	errata_n2_2138953_wa
 #endif
 
+#if ERRATA_N2_2242415
+	mov	x0, x18
+	bl	errata_n2_2242415_wa
+#endif
+
+#if ERRATA_N2_2138958
+	mov	x0, x18
+	bl	errata_n2_2138958_wa
+#endif
+
+#if ERRATA_N2_2242400
+	mov	x0, x18
+	bl	errata_n2_2242400_wa
+#endif
+
+#if ERRATA_N2_2280757
+	mov	x0, x18
+	bl	errata_n2_2280757_wa
+#endif
+
 #if ENABLE_AMU
 	/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
 	mrs	x0, cptr_el3
@@ -324,6 +465,10 @@ func neoverse_n2_errata_report
 	report_errata ERRATA_N2_2189731, neoverse_n2, 2189731
 	report_errata ERRATA_N2_2138956, neoverse_n2, 2138956
 	report_errata ERRATA_N2_2138953, neoverse_n2, 2138953
+	report_errata ERRATA_N2_2242415, neoverse_n2, 2242415
+	report_errata ERRATA_N2_2138958, neoverse_n2, 2138958
+	report_errata ERRATA_N2_2242400, neoverse_n2, 2242400
+	report_errata ERRATA_N2_2280757, neoverse_n2, 2280757
 
 	ldp	x8, x30, [sp], #16
 	ret
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
index 200f67de3..62a7a30cd 100644
--- a/lib/cpus/aarch64/neoverse_v1.S
+++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -288,6 +288,43 @@ func check_errata_2108267
 	b	cpu_rev_var_ls
 endfunc check_errata_2108267
 
+	/* --------------------------------------------------
+	 * Errata Workaround for Neoverse V1 Errata #2216392.
+	 * This applies to revisions r1p0 and r1p1 and is
+	 * still open.
+	 * This issue is also present in r0p0 but there is no
+	 * workaround in that revision.
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0-x17
+	 * --------------------------------------------------
+	 */
+func errata_neoverse_v1_2216392_wa
+	/* Check workaround compatibility. */
+	mov	x17, x30
+	bl	check_errata_2216392
+	cbz	x0, 1f
+
+	ldr	x0, =0x5
+	msr	S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
+	ldr	x0, =0x10F600E000
+	msr	S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */
+	ldr	x0, =0x10FF80E000
+	msr	S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
+	ldr	x0, =0x80000000003FF
+	msr	S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */
+
+	isb
+1:
+	ret	x17
+endfunc errata_neoverse_v1_2216392_wa
+
+func check_errata_2216392
+	/* Applies to revisions r1p0 and r1p1. */
+	mov	x1, #CPU_REV(1, 0)
+	mov	x2, #CPU_REV(1, 1)
+	b	cpu_rev_var_range
+endfunc check_errata_2216392
+
 	/* ---------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * ---------------------------------------------
@@ -326,6 +363,7 @@ func neoverse_v1_errata_report
 	report_errata ERRATA_V1_1966096, neoverse_v1, 1966096
 	report_errata ERRATA_V1_2139242, neoverse_v1, 2139242
 	report_errata ERRATA_V1_2108267, neoverse_v1, 2108267
+	report_errata ERRATA_V1_2216392, neoverse_v1, 2216392
 
 	ldp	x8, x30, [sp], #16
 	ret
@@ -379,6 +417,11 @@ func neoverse_v1_reset_func
 	bl	errata_neoverse_v1_2108267_wa
 #endif
 
+#if ERRATA_V1_2216392
+	mov	x0, x18
+	bl	errata_neoverse_v1_2216392_wa
+#endif
+
 	ret	x19
 endfunc neoverse_v1_reset_func
 
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 138f7a572..a5b8aae29 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -311,25 +311,30 @@ ERRATA_A78_1941498	?=0
 # well but there is no workaround for that revision.
 ERRATA_A78_1951500	?=0
 
-# Flag to apply erratum 1941500 workaround during reset. This erratum applies
-# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
-ERRATA_A78_AE_1941500	?=0
-
-# Flag to apply erratum 1951502 workaround during reset. This erratum applies
-# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
-ERRATA_A78_AE_1951502	?=0
-
 # Flag to apply erratum 1821534 workaround during reset. This erratum applies
 # to revisions r0p0 and r1p0 of the A78 cpu.
 ERRATA_A78_1821534	?=0
 
 # Flag to apply erratum 1952683 workaround during reset. This erratum applies
 # to revision r0p0 of the A78 cpu and was fixed in the revision r1p0.
-ERRATA_A78_1952683	?=0
+ERRATA_A78_1952683  ?=0
 
 # Flag to apply erratum 2132060 workaround during reset. This erratum applies
 # to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open.
-ERRATA_A78_2132060	?=0
+ERRATA_A78_2132060  ?=0
+
+# Flag to apply erratum 2242635 workaround during reset. This erratum applies
+# to revisions r1p0, r1p1, and r1p2 of the A78 cpu and is open. The issue is
+# present in r0p0 as well but there is no workaround for that revision.
+ERRATA_A78_2242635	?=0
+
+# Flag to apply erratum 1941500 workaround during reset. This erratum applies
+# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
+ERRATA_A78_AE_1941500	?=0
+
+# Flag to apply erratum 1951502 workaround during reset. This erratum applies
+# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
+ERRATA_A78_AE_1951502	?=0
 
 # Flag to apply T32 CLREX workaround during reset. This erratum applies
 # only to r0p0 and r1p0 of the Neoverse N1 cpu.
@@ -425,6 +430,11 @@ ERRATA_V1_2139242	?=0
 # to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open.
 ERRATA_V1_2108267	?=0
 
+# Flag to apply erratum 2216392 workaround during reset. This erratum applies
+# to revisions r1p0 and r1p1 of the Neoverse V1 cpu and is still open. This
+# issue exists in r0p0 as well but there is no workaround for that revision.
+ERRATA_V1_2216392	?=0
+
 # Flag to apply erratum 1987031 workaround during reset. This erratum applies
 # to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
 ERRATA_A710_1987031	?=0
@@ -461,6 +471,22 @@ ERRATA_N2_2138956	?=0
 # to revision r0p0 of the Neoverse N2 cpu and is still open.
 ERRATA_N2_2138953	?=0
 
+# Flag to apply erratum 2242415 workaround during reset. This erratum applies
+# to revision r0p0 of the Neoverse N2 cpu and is still open.
+ERRATA_N2_2242415	?=0
+
+# Flag to apply erratum 2138958 workaround during reset. This erratum applies
+# to revision r0p0 of the Neoverse N2 cpu and is still open.
+ERRATA_N2_2138958	?=0
+
+# Flag to apply erratum 2242400 workaround during reset. This erratum applies
+# to revision r0p0 of the Neoverse N2 cpu and is still open.
+ERRATA_N2_2242400	?=0
+
+# Flag to apply erratum 2280757 workaround during reset. This erratum applies
+# to revision r0p0 of the Neoverse N2 cpu and is still open.
+ERRATA_N2_2280757	?=0
+
 # Flag to apply erratum 2055002 workaround during reset. This erratum applies
 # to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open.
 ERRATA_A710_2055002	?=0
@@ -714,14 +740,6 @@ $(eval $(call add_define,ERRATA_A78_1941498))
 $(eval $(call assert_boolean,ERRATA_A78_1951500))
 $(eval $(call add_define,ERRATA_A78_1951500))
 
-# Process ERRATA_A78_AE_1941500 flag
-$(eval $(call assert_boolean,ERRATA_A78_AE_1941500))
-$(eval $(call add_define,ERRATA_A78_AE_1941500))
-
-# Process ERRATA_A78_AE_1951502 flag
-$(eval $(call assert_boolean,ERRATA_A78_AE_1951502))
-$(eval $(call add_define,ERRATA_A78_AE_1951502))
-
 # Process ERRATA_A78_1821534 flag
 $(eval $(call assert_boolean,ERRATA_A78_1821534))
 $(eval $(call add_define,ERRATA_A78_1821534))
@@ -734,6 +752,18 @@ $(eval $(call add_define,ERRATA_A78_1952683))
 $(eval $(call assert_boolean,ERRATA_A78_2132060))
 $(eval $(call add_define,ERRATA_A78_2132060))
 
+# Process ERRATA_A78_2242635 flag
+$(eval $(call assert_boolean,ERRATA_A78_2242635))
+$(eval $(call add_define,ERRATA_A78_2242635))
+
+# Process ERRATA_A78_AE_1941500 flag
+$(eval $(call assert_boolean,ERRATA_A78_AE_1941500))
+$(eval $(call add_define,ERRATA_A78_AE_1941500))
+
+# Process ERRATA_A78_AE_1951502 flag
+$(eval $(call assert_boolean,ERRATA_A78_AE_1951502))
+$(eval $(call add_define,ERRATA_A78_AE_1951502))
+
 # Process ERRATA_N1_1043202 flag
 $(eval $(call assert_boolean,ERRATA_N1_1043202))
 $(eval $(call add_define,ERRATA_N1_1043202))
@@ -826,6 +856,10 @@ $(eval $(call add_define,ERRATA_V1_2139242))
 $(eval $(call assert_boolean,ERRATA_V1_2108267))
 $(eval $(call add_define,ERRATA_V1_2108267))
 
+# Process ERRATA_V1_2216392 flag
+$(eval $(call assert_boolean,ERRATA_V1_2216392))
+$(eval $(call add_define,ERRATA_V1_2216392))
+
 # Process ERRATA_A710_1987031 flag
 $(eval $(call assert_boolean,ERRATA_A710_1987031))
 $(eval $(call add_define,ERRATA_A710_1987031))
@@ -862,6 +896,22 @@ $(eval $(call add_define,ERRATA_N2_2138956))
 $(eval $(call assert_boolean,ERRATA_N2_2138953))
 $(eval $(call add_define,ERRATA_N2_2138953))
 
+# Process ERRATA_N2_2242415 flag
+$(eval $(call assert_boolean,ERRATA_N2_2242415))
+$(eval $(call add_define,ERRATA_N2_2242415))
+
+# Process ERRATA_N2_2138958 flag
+$(eval $(call assert_boolean,ERRATA_N2_2138958))
+$(eval $(call add_define,ERRATA_N2_2138958))
+
+# Process ERRATA_N2_2242400 flag
+$(eval $(call assert_boolean,ERRATA_N2_2242400))
+$(eval $(call add_define,ERRATA_N2_2242400))
+
+# Process ERRATA_N2_2280757 flag
+$(eval $(call assert_boolean,ERRATA_N2_2280757))
+$(eval $(call add_define,ERRATA_N2_2280757))
+
 # Process ERRATA_A710_2055002 flag
 $(eval $(call assert_boolean,ERRATA_A710_2055002))
 $(eval $(call add_define,ERRATA_A710_2055002))