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| author | Manish Pandey <manish.pandey2@arm.com> | 2020-01-07 17:51:15 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2020-01-07 17:51:15 +0000 |
| commit | 8849298cb3ebd19377e61266e6c2f42eb2aea0f0 (patch) | |
| tree | d9b7fb3d7edfc57a770275c101f18cd025afa706 /plat/arm | |
| parent | eafdc55859b687af4f26613819a940bc4e4710ca (diff) | |
| parent | 786890caaeb3e3d01a3a5986a4e4af104c510e62 (diff) | |
| download | arm-trusted-firmware-8849298cb3ebd19377e61266e6c2f42eb2aea0f0.tar.gz | |
Merge "A5DS: Correct system freq, Cache Writeback Granule" into integration
Diffstat (limited to 'plat/arm')
| -rw-r--r-- | plat/arm/board/a5ds/include/platform_def.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/plat/arm/board/a5ds/include/platform_def.h b/plat/arm/board/a5ds/include/platform_def.h index d200af686..8559101ec 100644 --- a/plat/arm/board/a5ds/include/platform_def.h +++ b/plat/arm/board/a5ds/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019, Arm Limited. All rights reserved. + * Copyright (c) 2019-2020, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -47,7 +47,7 @@ #define A5_PERIPHERALS_BASE 0x1c000000 #define A5_PERIPHERALS_SIZE 0x10000 -#define ARM_CACHE_WRITEBACK_SHIFT 6 +#define ARM_CACHE_WRITEBACK_SHIFT 5 #define ARM_IRQ_SEC_PHY_TIMER 29 @@ -162,7 +162,7 @@ ARM_BL_REGIONS) /* Memory mapped Generic timer interfaces */ -#define A5DS_TIMER_BASE_FREQUENCY UL(24000000) +#define A5DS_TIMER_BASE_FREQUENCY UL(7500000) #define ARM_CONSOLE_BAUDRATE 115200 @@ -310,15 +310,15 @@ * PL011 related constants */ #define PLAT_ARM_BOOT_UART_BASE 0x1A200000 -#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 24000000 +#define PLAT_ARM_BOOT_UART_CLK_IN_HZ UL(7500000) #define PLAT_ARM_RUN_UART_BASE 0x1A210000 -#define PLAT_ARM_RUN_UART_CLK_IN_HZ 24000000 +#define PLAT_ARM_RUN_UART_CLK_IN_HZ UL(7500000) #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ -#define A5DS_TIMER_BASE_FREQUENCY UL(24000000) +#define A5DS_TIMER_BASE_FREQUENCY UL(7500000) /* System timer related constants */ #define PLAT_ARM_NSTIMER_FRAME_ID 1 |