diff options
author | Konstantin Porotchkin <kostap@marvell.com> | 2021-03-07 13:12:31 +0200 |
---|---|---|
committer | Manish Pandey <manish.pandey2@arm.com> | 2021-04-20 13:00:12 +0200 |
commit | 90eac1703d555cc007f145ce4c941a2bc6bf58c5 (patch) | |
tree | 96dd7a08a218ae6cc7dd8e59598415056a0c8b9b /plat/marvell/armada/a8k/common | |
parent | 2e1dba44fded455a38b3870998286ab16bc4237e (diff) | |
download | arm-trusted-firmware-90eac1703d555cc007f145ce4c941a2bc6bf58c5.tar.gz |
plat/marvell: a8k: move efuse definitions to separate header
Move efuse definitions to a separate header file for later
usage with other FW modules.
Change-Id: I2e9465f760d0388c8e5863bc64a4cdc57de2417f
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/47313
Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
Reviewed-by: Yi Guo <yi.guo@cavium.com>
Diffstat (limited to 'plat/marvell/armada/a8k/common')
-rw-r--r-- | plat/marvell/armada/a8k/common/include/a8k_plat_def.h | 3 | ||||
-rw-r--r-- | plat/marvell/armada/a8k/common/plat_ble_setup.c | 26 |
2 files changed, 9 insertions, 20 deletions
diff --git a/plat/marvell/armada/a8k/common/include/a8k_plat_def.h b/plat/marvell/armada/a8k/common/include/a8k_plat_def.h index de8031536..3a0fd4b9d 100644 --- a/plat/marvell/armada/a8k/common/include/a8k_plat_def.h +++ b/plat/marvell/armada/a8k/common/include/a8k_plat_def.h @@ -64,7 +64,8 @@ #define MVEBU_AP_GPIO_DATA_IN (MVEBU_AP_GPIO_REGS + 0x10) #define MVEBU_AP_I2C_BASE (MVEBU_REGS_BASE + 0x511000) #define MVEBU_CP0_I2C_BASE (MVEBU_CP_REGS_BASE(0) + 0x701000) -#define MVEBU_AP_EXT_TSEN_BASE (MVEBU_RFU_BASE + 0x8084) +#define MVEBU_AP_GEN_MGMT_BASE (MVEBU_RFU_BASE + 0x8000) +#define MVEBU_AP_EXT_TSEN_BASE (MVEBU_AP_GEN_MGMT_BASE + 0x84) #define MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap, win) (MVEBU_REGS_BASE_AP(ap) + \ 0x20080 + ((win) * 0x8)) diff --git a/plat/marvell/armada/a8k/common/plat_ble_setup.c b/plat/marvell/armada/a8k/common/plat_ble_setup.c index 59a3a3ae1..9c5ee153a 100644 --- a/plat/marvell/armada/a8k/common/plat_ble_setup.c +++ b/plat/marvell/armada/a8k/common/plat_ble_setup.c @@ -14,6 +14,7 @@ #include <drivers/marvell/mochi/cp110_setup.h> #include <armada_common.h> +#include <efuse_def.h> #include <mv_ddr_if.h> #include <mvebu_def.h> #include <plat_marvell.h> @@ -27,7 +28,6 @@ #define MMAP_RESTORE_SAVED 1 /* SAR clock settings */ -#define MVEBU_AP_GEN_MGMT_BASE (MVEBU_RFU_BASE + 0x8000) #define MVEBU_AP_SAR_REG_BASE(r) (MVEBU_AP_GEN_MGMT_BASE + 0x200 +\ ((r) << 2)) @@ -82,11 +82,6 @@ (0x1 << AVS_SOFT_RESET_OFFSET) | \ (0x1 << AVS_ENABLE_OFFSET)) -#define MVEBU_AP_EFUSE_SRV_CTRL_REG (MVEBU_AP_GEN_MGMT_BASE + 0x8) -#define EFUSE_SRV_CTRL_LD_SELECT_OFFS 6 -#define EFUSE_SRV_CTRL_LD_SEL_USER_MASK (1 << EFUSE_SRV_CTRL_LD_SELECT_OFFS) - - /* * - Identification information in the LD-0 eFuse: * DRO: LD0[74:65] - Not used by the SW @@ -96,14 +91,7 @@ * Cluster 1 PWR: LD0[193] - if set to 1, power down CPU Cluster-1 * resulting in 2 CPUs active only (7020) */ -#define MVEBU_AP_LD_EFUSE_BASE (MVEBU_AP_GEN_MGMT_BASE + 0xF00) -/* Bits [94:63] - 32 data bits total */ -#define MVEBU_AP_LD0_94_63_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x8) -/* Bits [125:95] - 31 data bits total, 32nd bit is parity for bits [125:63] */ -#define MVEBU_AP_LD0_125_95_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0xC) -/* Bits [220:189] - 32 data bits total */ -#define MVEBU_AP_LD0_220_189_EFUSE_OFFS (MVEBU_AP_LD_EFUSE_BASE + 0x18) -/* Offsets for the above 2 fields combined into single 64-bit value [125:63] */ +/* Offsets for 2 efuse fields combined into single 64-bit value [125:63] */ #define EFUSE_AP_LD0_DRO_OFFS 2 /* LD0[74:65] */ #define EFUSE_AP_LD0_DRO_MASK 0x3FF #define EFUSE_AP_LD0_REVID_OFFS 12 /* LD0[78:75] */ @@ -376,20 +364,20 @@ static void ble_plat_svc_config(void) uint8_t avs_data_bits, min_sw_ver, svc_fields; unsigned int ap_type; - /* Set access to LD0 */ + /* Get test EERPOM data */ avs_workpoint = avs_update_from_eeprom(0); if (avs_workpoint) goto set_aws_wp; /* Set access to LD0 */ reg_val = mmio_read_32(MVEBU_AP_EFUSE_SRV_CTRL_REG); - reg_val &= ~EFUSE_SRV_CTRL_LD_SEL_USER_MASK; + reg_val &= ~EFUSE_SRV_CTRL_LD_SELECT_MASK; mmio_write_32(MVEBU_AP_EFUSE_SRV_CTRL_REG, reg_val); /* Obtain the value of LD0[125:63] */ - efuse = mmio_read_32(MVEBU_AP_LD0_125_95_EFUSE_OFFS); + efuse = mmio_read_32(MVEBU_AP_LDX_125_95_EFUSE_OFFS); efuse <<= 32; - efuse |= mmio_read_32(MVEBU_AP_LD0_94_63_EFUSE_OFFS); + efuse |= mmio_read_32(MVEBU_AP_LDX_94_63_EFUSE_OFFS); /* SW Revision: * Starting from SW revision 1 the SVC flow is supported. @@ -452,7 +440,7 @@ static void ble_plat_svc_config(void) perr[i] = 1; /* register the error */ } - single_cluster = mmio_read_32(MVEBU_AP_LD0_220_189_EFUSE_OFFS); + single_cluster = mmio_read_32(MVEBU_AP_LDX_220_189_EFUSE_OFFS); single_cluster = (single_cluster >> EFUSE_AP_LD0_CLUSTER_DOWN_OFFS) & 1; device_id = cp110_device_id_get(MVEBU_CP_REGS_BASE(0)); |