diff options
| author | Grzegorz Jaszczyk <jaz@semihalf.com> | 2020-01-03 09:35:21 +0100 |
|---|---|---|
| committer | Manish Pandey <manish.pandey2@arm.com> | 2021-04-20 12:59:40 +0200 |
| commit | 81c2a044e2d8cb06c66c44300741d449b969fcf1 (patch) | |
| tree | dbdd1fd268d5239289017d2d10e620c1db1e8015 /plat/marvell/armada | |
| parent | b81444e84382eaa6dca194c9542769670b0712f1 (diff) | |
| download | arm-trusted-firmware-81c2a044e2d8cb06c66c44300741d449b969fcf1.tar.gz | |
drivers: marvell: add support for secure read/write of dfx register-set
Since the dfx register set is going to be marked as secure expose dfx
secure read and write function via SiP services. In introduced misc_dfx
driver some registers are white-listed so non-secure software can still
access them.
This will allow non-secure word drivers access some white-listed
registers related to e.g.: Sample at reset, efuses, SoC type and
revision ID accesses.
Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/25055
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Diffstat (limited to 'plat/marvell/armada')
| -rw-r--r-- | plat/marvell/armada/a8k/common/a8k_common.mk | 1 | ||||
| -rw-r--r-- | plat/marvell/armada/common/mrvl_sip_svc.c | 5 |
2 files changed, 6 insertions, 0 deletions
diff --git a/plat/marvell/armada/a8k/common/a8k_common.mk b/plat/marvell/armada/a8k/common/a8k_common.mk index dcb64ce0f..3acc3b4cf 100644 --- a/plat/marvell/armada/a8k/common/a8k_common.mk +++ b/plat/marvell/armada/a8k/common/a8k_common.mk @@ -116,6 +116,7 @@ MARVELL_DRV := $(MARVELL_DRV_BASE)/io_win.c \ $(MARVELL_DRV_BASE)/mc_trustzone/mc_trustzone.c \ $(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c \ $(MARVELL_DRV_BASE)/secure_dfx_access/armada_thermal.c \ + $(MARVELL_DRV_BASE)/secure_dfx_access/misc_dfx.c \ $(MARVELL_DRV_BASE)/ddr_phy_access.c \ drivers/rambus/trng_ip_76.c diff --git a/plat/marvell/armada/common/mrvl_sip_svc.c b/plat/marvell/armada/common/mrvl_sip_svc.c index ebc7632ac..48172b286 100644 --- a/plat/marvell/armada/common/mrvl_sip_svc.c +++ b/plat/marvell/armada/common/mrvl_sip_svc.c @@ -147,6 +147,11 @@ uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid, ret = mvebu_dfx_thermal_handle(x1, &read, x2, x3); SMC_RET2(handle, ret, read); } + if (x1 >= MV_SIP_DFX_SREAD && x1 <= MV_SIP_DFX_SWRITE) { + ret = mvebu_dfx_misc_handle(x1, &read, x2, x3); + SMC_RET2(handle, ret, read); + } + SMC_RET1(handle, SMC_UNK); case MV_SIP_DDR_PHY_WRITE: ret = mvebu_ddr_phy_write(x1, x2); |