diff options
| author | Grzegorz Jaszczyk <jaz@semihalf.com> | 2019-12-18 15:58:27 +0100 |
|---|---|---|
| committer | Manish Pandey <manish.pandey2@arm.com> | 2021-04-20 12:59:18 +0200 |
| commit | ad416958d946c66fdc116a5982eb8eb7e747e520 (patch) | |
| tree | b6a545537ab0129211edf7212a9664f07369bbb6 /plat/marvell | |
| parent | dceac436f620e60cd0149194377871b225216079 (diff) | |
| download | arm-trusted-firmware-ad416958d946c66fdc116a5982eb8eb7e747e520.tar.gz | |
drivers: marvell: add thermal sensor driver and expose it via SIP service
Since the dfx register set is going to be marked as secure (in order to
protect efuse registers for non secure access), accessing thermal
registers which are part of dfx register set, will not be possible from
lower exception levels. Due to above expose thermal driver as a SiP
service. This will allow Linux and U-Boot thermal driver to initialise
and perform various operations on thermal sensor.
The thermal sensor driver is based on Linux
drivers/thermal/armada_thermal.c.
Change-Id: I4763a3bf5c43750c724c86b1dcadad3cb729e93e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-on: https://sj1git1.cavium.com/20581
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: Kostya Porotchkin <kostap@marvell.com>
Diffstat (limited to 'plat/marvell')
| -rw-r--r-- | plat/marvell/armada/a8k/common/a8k_common.mk | 7 | ||||
| -rw-r--r-- | plat/marvell/armada/common/mrvl_sip_svc.c | 7 |
2 files changed, 10 insertions, 4 deletions
diff --git a/plat/marvell/armada/a8k/common/a8k_common.mk b/plat/marvell/armada/a8k/common/a8k_common.mk index 8a463eafe..e20cf788a 100644 --- a/plat/marvell/armada/a8k/common/a8k_common.mk +++ b/plat/marvell/armada/a8k/common/a8k_common.mk @@ -112,9 +112,10 @@ MARVELL_DRV := $(MARVELL_DRV_BASE)/io_win.c \ $(MARVELL_DRV_BASE)/amb_adec.c \ $(MARVELL_DRV_BASE)/ccu.c \ $(MARVELL_DRV_BASE)/cache_llc.c \ - $(MARVELL_DRV_BASE)/comphy/phy-comphy-cp110.c \ - $(MARVELL_DRV_BASE)/mc_trustzone/mc_trustzone.c \ - $(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c \ + $(MARVELL_DRV_BASE)/comphy/phy-comphy-cp110.c \ + $(MARVELL_DRV_BASE)/mc_trustzone/mc_trustzone.c \ + $(MARVELL_DRV_BASE)/mg_conf_cm3/mg_conf_cm3.c \ + $(MARVELL_DRV_BASE)/secure_dfx_access/armada_thermal.c \ drivers/rambus/trng_ip_76.c BL31_PORTING_SOURCES := $(BOARD_DIR)/board/marvell_plat_config.c diff --git a/plat/marvell/armada/common/mrvl_sip_svc.c b/plat/marvell/armada/common/mrvl_sip_svc.c index 64187fb48..bdf79b211 100644 --- a/plat/marvell/armada/common/mrvl_sip_svc.c +++ b/plat/marvell/armada/common/mrvl_sip_svc.c @@ -16,6 +16,7 @@ #include <plat_marvell.h> #include "comphy/phy-comphy-cp110.h" +#include "secure_dfx_access/dfx.h" #include <stdbool.h> /* #define DEBUG_COMPHY */ @@ -37,6 +38,7 @@ #define MV_SIP_LLC_ENABLE 0x82000011 #define MV_SIP_PMU_IRQ_ENABLE 0x82000012 #define MV_SIP_PMU_IRQ_DISABLE 0x82000013 +#define MV_SIP_DFX 0x82000014 /* TRNG */ #define MV_SIP_RNG_64 0xC200FF11 @@ -71,7 +73,7 @@ uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid, void *handle, u_register_t flags) { - u_register_t ret; + u_register_t ret, read; uint32_t w2[2] = {0, 0}; int i; @@ -136,6 +138,9 @@ uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid, mvebu_pmu_interrupt_disable(); SMC_RET1(handle, 0); #endif + case MV_SIP_DFX: + ret = mvebu_dfx_handle(x1, &read, x2, x3); + SMC_RET2(handle, ret, read); case MV_SIP_RNG_64: ret = eip76_rng_get_random((uint8_t *)&w2, 4 * (x1 % 2 + 1)); SMC_RET3(handle, ret, w2[0], w2[1]); |