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| author | Varun Wadekar <vwadekar@nvidia.com> | 2018-05-17 10:10:25 -0700 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2020-01-31 13:19:38 -0800 |
| commit | e44f86ef2b01a71e78ce959d3dcfa354cf259c0f (patch) | |
| tree | 02cedb6c912b04b1e95975dc49e8a441c3e670ba /plat/nvidia/tegra/soc/t132 | |
| parent | 39171cd0337be4c9bea14eb8f7f6cc583ea29ea4 (diff) | |
| download | arm-trusted-firmware-e44f86ef2b01a71e78ce959d3dcfa354cf259c0f.tar.gz | |
Tegra: remove weakly defined PSCI platform handlers
This patch removes all the weakly defined PSCI handlers defined
per-platform, to improve code coverage numbers and reduce MISRA
defects.
Change-Id: I0f9c0caa0a6071d0360d07454b19dcc7340da8c2
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'plat/nvidia/tegra/soc/t132')
| -rw-r--r-- | plat/nvidia/tegra/soc/t132/plat_psci_handlers.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c b/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c index bd3f46fcc..584031204 100644 --- a/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c +++ b/plat/nvidia/tegra/soc/t132/plat_psci_handlers.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -35,6 +36,30 @@ static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; +plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl, + const plat_local_state_t *states, + uint32_t ncpu) +{ + plat_local_state_t target = PLAT_MAX_OFF_STATE, temp; + uint32_t num_cpu = ncpu; + const plat_local_state_t *local_state = states; + + (void)lvl; + + assert(ncpu != 0U); + + do { + temp = *local_state; + if ((temp < target)) { + target = temp; + } + --num_cpu; + local_state++; + } while (num_cpu != 0U); + + return target; +} + int32_t tegra_soc_validate_power_state(unsigned int power_state, psci_power_state_t *req_state) { @@ -112,6 +137,12 @@ int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state) return PSCI_E_SUCCESS; } +int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state) +{ + (void)cpu_state; + return PSCI_E_SUCCESS; +} + int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) { uint64_t val; @@ -139,6 +170,16 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) return PSCI_E_SUCCESS; } +int32_t tegra_soc_pwr_domain_suspend_pwrdown_early(const psci_power_state_t *target_state) +{ + return PSCI_E_NOT_SUPPORTED; +} + +int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) +{ + return PSCI_E_SUCCESS; +} + int tegra_soc_prepare_system_reset(void) { /* @@ -154,3 +195,9 @@ int tegra_soc_prepare_system_reset(void) return PSCI_E_SUCCESS; } + +__dead2 void tegra_soc_prepare_system_off(void) +{ + ERROR("Tegra System Off: operation not handled.\n"); + panic(); +} |