diff options
| author | Lin Huang <hl@rock-chips.com> | 2017-05-16 16:40:46 +0800 |
|---|---|---|
| committer | Caesar Wang <wxt@rock-chips.com> | 2017-06-08 09:59:53 +0800 |
| commit | 4e836d3578a6817756a320022f0595ec2ee50f3f (patch) | |
| tree | f91249e32626780de0a01f09e4e0bafd74813fed /plat/rockchip/common | |
| parent | af27fb89a9b755eb7adb65f52027f78d5c7a461a (diff) | |
| download | arm-trusted-firmware-4e836d3578a6817756a320022f0595ec2ee50f3f.tar.gz | |
rockchip/rk3399: enable PMU_PERILP_PD_EN bit when suspend
with PMU_PERILP_PD_EN bit enable, the soc will shutdown
cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con,
spi, i2c, uart, saradc, tsadc when suspend, we have M0 code
need to run when suspend in normal SRAM, so we need to take
care of that.
Change-Id: I8c066637e5b81d4b1d53197450b9d592cbe00793
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Diffstat (limited to 'plat/rockchip/common')
| -rw-r--r-- | plat/rockchip/common/include/plat_private.h | 2 | ||||
| -rw-r--r-- | plat/rockchip/common/pmusram/pmu_sram_cpus_on.S | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h index f0aee0877..b9540f23e 100644 --- a/plat/rockchip/common/include/plat_private.h +++ b/plat/rockchip/common/include/plat_private.h @@ -24,7 +24,9 @@ extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end; extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end; extern uint32_t __bl31_sram_stack_start, __bl31_sram_stack_end; +extern uint32_t __bl31_sram_text_real_end, __bl31_sram_data_real_end; extern uint32_t __sram_incbin_start, __sram_incbin_end; +extern uint32_t __sram_incbin_real_end; /****************************************************************************** diff --git a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S index 64261ac00..06dfea95b 100644 --- a/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S +++ b/plat/rockchip/common/pmusram/pmu_sram_cpus_on.S @@ -25,7 +25,7 @@ ddr_resume: mov sp, x2 bl dmc_restore #endif - + bl sram_restore sys_resume: bl psci_entrypoint endfunc pmu_cpuson_entrypoint |