Merge changes Id7bdbc9b,Ia813e051,I2c437380,I736724cc,I454fb40a, ... into integration

* changes:
  renesas: rzg: Add support to identify EK874 RZ/G2E board
  drivers: renesas: common: watchdog: Add support for RZ/G2E
  drivers: renesas: rzg: Add QoS support for RZ/G2E
  drivers: renesas: rzg: Add PFC support for RZ/G2E
  drivers: renesas: common: Add support for DRAM initialization on RZ/G2E SoC
  renesas: rzg: Add support to identify HopeRun HiHope RZ/G2N board
  drivers: renesas: common: emmc: Select eMMC channel for RZ/G2N SoC
  drivers: renesas: rzg: Add QoS support for RZ/G2N
  drivers: renesas: rzg: Add PFC support for RZ/G2N
  drivers: renesas: common: Add support for DRAM initialization on RZ/G2N SoC
  renesas: rzg: Add support to identify HopeRun HiHope RZ/G2H board
  drivers: renesas: common: emmc: Select eMMC channel for RZ/G2H SoC
  drivers: renesas: rzg: Add QoS support for RZ/G2H
  drivers: renesas: rzg: Add PFC support for RZ/G2H
  drivers: renesas: common: Add support for DRAM initialization on RZ/G2H SoC
  drivers: renesas: rzg: Switch using common ddr code
  drivers: renesas: ddr: Move to common

5 files changed, 191 insertions, 22 deletions

diff --git a/plat/renesas/common/bl2_cpg_init.c b/plat/renesas/common/bl2_cpg_init.c
index 677a57d04..ba8e53b58 100644
--- a/plat/renesas/common/bl2_cpg_init.c
+++ b/plat/renesas/common/bl2_cpg_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -13,7 +13,8 @@
 
 static void bl2_secure_cpg_init(void);
 
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || \
+	(RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
 static void bl2_realtime_cpg_init_h3(void);
 static void bl2_system_cpg_init_h3(void);
 #endif
@@ -23,7 +24,7 @@ static void bl2_realtime_cpg_init_m3(void);
 static void bl2_system_cpg_init_m3(void);
 #endif
 
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N) || (RCAR_LSI == RZ_G2N)
 static void bl2_realtime_cpg_init_m3n(void);
 static void bl2_system_cpg_init_m3n(void);
 #endif
@@ -33,7 +34,7 @@ static void bl2_realtime_cpg_init_v3m(void);
 static void bl2_system_cpg_init_v3m(void);
 #endif
 
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
 static void bl2_realtime_cpg_init_e3(void);
 static void bl2_system_cpg_init_e3(void);
 #endif
@@ -57,7 +58,7 @@ static void bl2_secure_cpg_init(void)
 #if (RCAR_LSI == RCAR_D3)
 	reset_cr2 = 0x00000000U;
 	stop_cr2 = 0xFFFFFFFFU;
-#elif (RCAR_LSI == RCAR_E3)
+#elif (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
 	reset_cr2 = 0x10000000U;
 	stop_cr2 = 0xEFFFFFFFU;
 #else
@@ -106,7 +107,8 @@ static void bl2_secure_cpg_init(void)
 	cpg_write(SCSRSTECR11, 0x00000000U);
 }
 
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_H3) || \
+	(RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
 static void bl2_realtime_cpg_init_h3(void)
 {
 	uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
@@ -185,7 +187,7 @@ static void bl2_system_cpg_init_m3(void)
 }
 #endif
 
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_M3N)  || (RCAR_LSI == RZ_G2N)
 static void bl2_realtime_cpg_init_m3n(void)
 {
 	/* Realtime Module Stop Control Registers */
@@ -253,7 +255,7 @@ static void bl2_system_cpg_init_v3m(void)
 }
 #endif
 
-#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3)
+#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
 static void bl2_realtime_cpg_init_e3(void)
 {
 	/* Realtime Module Stop Control Registers */
@@ -360,15 +362,15 @@ void bl2_cpg_init(void)
 			panic();
 			break;
 		}
-#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
 		bl2_realtime_cpg_init_h3();
 #elif (RCAR_LSI == RCAR_M3) || (RCAR_LSI == RZ_G2M)
 		bl2_realtime_cpg_init_m3();
-#elif RCAR_LSI == RCAR_M3N
+#elif RCAR_LSI == RCAR_M3N || (RCAR_LSI == RZ_G2N)
 		bl2_realtime_cpg_init_m3n();
 #elif RCAR_LSI == RCAR_V3M
 		bl2_realtime_cpg_init_v3m();
-#elif RCAR_LSI == RCAR_E3
+#elif RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2E
 		bl2_realtime_cpg_init_e3();
 #elif RCAR_LSI == RCAR_D3
 		bl2_realtime_cpg_init_d3();
@@ -406,15 +408,15 @@ void bl2_system_cpg_init(void)
 		panic();
 		break;
 	}
-#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N)
+#elif (RCAR_LSI == RCAR_H3) || (RCAR_LSI == RCAR_H3N) || (RCAR_LSI == RZ_G2H)
 	bl2_system_cpg_init_h3();
 #elif (RCAR_LSI == RCAR_M3) || (RCAR_LSI == RZ_G2M)
 	bl2_system_cpg_init_m3();
-#elif RCAR_LSI == RCAR_M3N
+#elif RCAR_LSI == RCAR_M3N  || (RCAR_LSI == RZ_G2N)
 	bl2_system_cpg_init_m3n();
 #elif RCAR_LSI == RCAR_V3M
 	bl2_system_cpg_init_v3m();
-#elif RCAR_LSI == RCAR_E3
+#elif RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2E
 	bl2_system_cpg_init_e3();
 #elif RCAR_LSI == RCAR_D3
 	bl2_system_cpg_init_d3();
diff --git a/plat/renesas/common/common.mk b/plat/renesas/common/common.mk
index 984ab5bac..fafce9834 100644
--- a/plat/renesas/common/common.mk
+++ b/plat/renesas/common/common.mk
@@ -34,6 +34,9 @@ RCAR_D3:=5
 RCAR_V3M:=6
 RCAR_AUTO:=99
 RZ_G2M:=100
+RZ_G2H:=101
+RZ_G2N:=102
+RZ_G2E:=103
 $(eval $(call add_define,RCAR_H3))
 $(eval $(call add_define,RCAR_M3))
 $(eval $(call add_define,RCAR_M3N))
@@ -43,6 +46,9 @@ $(eval $(call add_define,RCAR_D3))
 $(eval $(call add_define,RCAR_V3M))
 $(eval $(call add_define,RCAR_AUTO))
 $(eval $(call add_define,RZ_G2M))
+$(eval $(call add_define,RZ_G2H))
+$(eval $(call add_define,RZ_G2N))
+$(eval $(call add_define,RZ_G2E))
 
 RCAR_CUT_10:=0
 RCAR_CUT_11:=1
diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk
index 5e4978c0a..7a7a56c79 100644
--- a/plat/renesas/rcar/platform.mk
+++ b/plat/renesas/rcar/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -293,12 +293,12 @@ ifeq (${RCAR_SYSTEM_RESET_KEEPON_DDR},1)
   endif
 endif
 
-include drivers/renesas/rcar/ddr/ddr.mk
+include drivers/renesas/common/ddr/ddr.mk
 include drivers/renesas/rcar/qos/qos.mk
 include drivers/renesas/rcar/pfc/pfc.mk
 include lib/libfdt/libfdt.mk
 
-PLAT_INCLUDES	+=	-Idrivers/renesas/rcar/ddr		\
+PLAT_INCLUDES	+=	-Idrivers/renesas/common/ddr		\
 			-Idrivers/renesas/rcar/qos		\
 			-Idrivers/renesas/rcar/board		\
 			-Idrivers/renesas/rcar/cpld/		\
diff --git a/plat/renesas/rzg/bl2_plat_setup.c b/plat/renesas/rzg/bl2_plat_setup.c
index 13f413b55..ccc2562ee 100644
--- a/plat/renesas/rzg/bl2_plat_setup.c
+++ b/plat/renesas/rzg/bl2_plat_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2020-2021, Renesas Electronics Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -78,12 +78,26 @@ static void bl2_init_generic_timer(void);
 #if RCAR_LSI == RZ_G2M
 #define TARGET_PRODUCT			PRR_PRODUCT_M3
 #define TARGET_NAME			"RZ/G2M"
+#elif RCAR_LSI == RZ_G2H
+#define TARGET_PRODUCT			PRR_PRODUCT_H3
+#define TARGET_NAME			"RZ/G2H"
+#elif RCAR_LSI == RZ_G2N
+#define TARGET_PRODUCT			PRR_PRODUCT_M3N
+#define TARGET_NAME			"RZ/G2N"
+#elif RCAR_LSI == RZ_G2E
+#define TARGET_PRODUCT			PRR_PRODUCT_E3
+#define TARGET_NAME			"RZ/G2E"
 #elif RCAR_LSI == RCAR_AUTO
 #define TARGET_NAME			"RZ/G2M"
 #endif /* RCAR_LSI == RZ_G2M */
 
+#if (RCAR_LSI == RZ_G2E)
+#define GPIO_INDT			(GPIO_INDT6)
+#define GPIO_BKUP_TRG_SHIFT		((uint32_t)1U << 13U)
+#else
 #define GPIO_INDT			(GPIO_INDT1)
 #define GPIO_BKUP_TRG_SHIFT		(1U << 8U)
+#endif /* RCAR_LSI == RZ_G2E */
 
 CASSERT((PARAMS_BASE + sizeof(bl2_to_bl31_params_mem_t) + 0x100)
 	 < (RCAR_SHARED_MEM_BASE + RCAR_SHARED_MEM_SIZE),
@@ -424,6 +438,18 @@ static void bl2_populate_compatible_string(void *dt)
 		ret = fdt_setprop_string(dt, 0, "compatible",
 					 "hoperun,hihope-rzg2m");
 		break;
+	case BOARD_HIHOPE_RZ_G2H:
+		ret = fdt_setprop_string(dt, 0, "compatible",
+					 "hoperun,hihope-rzg2h");
+		break;
+	case BOARD_HIHOPE_RZ_G2N:
+		ret = fdt_setprop_string(dt, 0, "compatible",
+					 "hoperun,hihope-rzg2n");
+		break;
+	case BOARD_EK874_RZ_G2E:
+		ret = fdt_setprop_string(dt, 0, "compatible",
+					 "si-linux,cat874");
+		break;
 	default:
 		NOTICE("BL2: Cannot set compatible string, board unsupported\n");
 		panic();
@@ -441,6 +467,18 @@ static void bl2_populate_compatible_string(void *dt)
 		ret = fdt_appendprop_string(dt, 0, "compatible",
 					    "renesas,r8a774a1");
 		break;
+	case PRR_PRODUCT_H3:
+		ret = fdt_appendprop_string(dt, 0, "compatible",
+					    "renesas,r8a774e1");
+		break;
+	case PRR_PRODUCT_M3N:
+		ret = fdt_appendprop_string(dt, 0, "compatible",
+					    "renesas,r8a774b1");
+		break;
+	case PRR_PRODUCT_E3:
+		ret = fdt_appendprop_string(dt, 0, "compatible",
+					    "renesas,r8a774c0");
+		break;
 	default:
 		NOTICE("BL2: Cannot set compatible string, SoC unsupported\n");
 		panic();
@@ -560,6 +598,42 @@ static void bl2_advertise_dram_size(uint32_t product)
 		dram_config[1] = 0x80000000ULL;
 		dram_config[5] = 0x80000000ULL;
 		break;
+	case PRR_PRODUCT_H3:
+#if (RCAR_DRAM_LPDDR4_MEMCONF == 0)
+		/* 4GB(1GBx4) */
+		dram_config[1] = 0x40000000ULL;
+		dram_config[3] = 0x40000000ULL;
+		dram_config[5] = 0x40000000ULL;
+		dram_config[7] = 0x40000000ULL;
+#elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 5) && \
+	(RCAR_DRAM_SPLIT == 2)
+		/* 4GB(2GBx2 2ch split) */
+		dram_config[1] = 0x80000000ULL;
+		dram_config[3] = 0x80000000ULL;
+#elif (RCAR_DRAM_LPDDR4_MEMCONF == 1) && (RCAR_DRAM_CHANNEL == 15)
+		/* 8GB(2GBx4: default) */
+		dram_config[1] = 0x80000000ULL;
+		dram_config[3] = 0x80000000ULL;
+		dram_config[5] = 0x80000000ULL;
+		dram_config[7] = 0x80000000ULL;
+#endif /* RCAR_DRAM_LPDDR4_MEMCONF == 0 */
+		break;
+	case PRR_PRODUCT_M3N:
+		/* 4GB(4GBx1) */
+		dram_config[1] = 0x100000000ULL;
+		break;
+	case PRR_PRODUCT_E3:
+#if (RCAR_DRAM_DDR3L_MEMCONF == 0)
+		/* 1GB(512MBx2) */
+		dram_config[1] = 0x40000000ULL;
+#elif (RCAR_DRAM_DDR3L_MEMCONF == 1)
+		/* 2GB(512MBx4) */
+		dram_config[1] = 0x80000000ULL;
+#elif (RCAR_DRAM_DDR3L_MEMCONF == 2)
+		/* 4GB(1GBx4) */
+		dram_config[1] = 0x100000000ULL;
+#endif /* RCAR_DRAM_DDR3L_MEMCONF == 0 */
+		break;
 	default:
 		NOTICE("BL2: Detected invalid DRAM entries\n");
 		break;
@@ -578,13 +652,23 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
 	const char *unknown = "unknown";
 	const char *cpu_ca57 = "CA57";
 	const char *cpu_ca53 = "CA53";
+	const char *product_g2e = "G2E";
+	const char *product_g2h = "G2H";
 	const char *product_g2m = "G2M";
+	const char *product_g2n = "G2N";
 	const char *boot_hyper80 = "HyperFlash(80MHz)";
 	const char *boot_qspi40 = "QSPI Flash(40MHz)";
 	const char *boot_qspi80 = "QSPI Flash(80MHz)";
 	const char *boot_emmc25x1 = "eMMC(25MHz x1)";
 	const char *boot_emmc50x8 = "eMMC(50MHz x8)";
+#if (RCAR_LSI == RZ_G2E)
+	uint32_t sscg;
+	const char *sscg_on = "PLL1 SSCG Clock select";
+	const char *sscg_off = "PLL1 nonSSCG Clock select";
+	const char *boot_hyper160 = "HyperFlash(150MHz)";
+#else
 	const char *boot_hyper160 = "HyperFlash(160MHz)";
+#endif /* RCAR_LSI == RZ_G2E */
 #if RZG_LCS_STATE_DETECTION_ENABLE
 	uint32_t lcs;
 	const char *lcs_secure = "SE";
@@ -646,6 +730,15 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
 	case PRR_PRODUCT_M3:
 		str = product_g2m;
 		break;
+	case PRR_PRODUCT_H3:
+		str = product_g2h;
+		break;
+	case PRR_PRODUCT_M3N:
+		str = product_g2n;
+		break;
+	case PRR_PRODUCT_E3:
+		str = product_g2e;
+		break;
 	default:
 		str = unknown;
 		break;
@@ -667,10 +760,22 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
 		NOTICE("BL2: PRR is RZ/%s Ver.%d.%d\n", str, major, minor);
 	}
 
+#if (RCAR_LSI == RZ_G2E)
+	if (product == PRR_PRODUCT_E3) {
+		reg = mmio_read_32(RCAR_MODEMR);
+		sscg = reg & RCAR_SSCG_MASK;
+		str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;
+		NOTICE("BL2: %s\n", str);
+	}
+#endif /* RCAR_LSI == RZ_G2E */
+
 	rzg_get_board_type(&type, &rev);
 
 	switch (type) {
 	case BOARD_HIHOPE_RZ_G2M:
+	case BOARD_HIHOPE_RZ_G2H:
+	case BOARD_HIHOPE_RZ_G2N:
+	case BOARD_EK874_RZ_G2E:
 		break;
 	default:
 		type = BOARD_UNKNOWN;
@@ -762,7 +867,7 @@ lcm_state:
 
 	if (boot_cpu == MODEMR_BOOT_CPU_CA57 ||
 	    boot_cpu == MODEMR_BOOT_CPU_CA53) {
-		ret = rzg_dram_init();
+		ret = rcar_dram_init();
 		if (ret != 0) {
 			NOTICE("BL2: Failed to DRAM initialize (%d).\n", ret);
 			panic();
@@ -884,6 +989,9 @@ void bl2_platform_setup(void)
 
 static void bl2_init_generic_timer(void)
 {
+#if RCAR_LSI == RZ_G2E
+	uint32_t reg_cntfid = EXTAL_EBISU;
+#else
 	uint32_t reg_cntfid;
 	uint32_t modemr;
 	uint32_t modemr_pll;
@@ -899,6 +1007,7 @@ static void bl2_init_generic_timer(void)
 
 	/* Set frequency data in CNTFID0 */
 	reg_cntfid = pll_table[modemr_pll >> MODEMR_BOOT_PLL_SHIFT];
+#endif /* RCAR_LSI == RZ_G2E */
 
 	/* Update memory mapped and register based frequency */
 	write_cntfrq_el0((u_register_t)reg_cntfid);
diff --git a/plat/renesas/rzg/platform.mk b/plat/renesas/rzg/platform.mk
index 421cbbe64..f37d7d0cc 100644
--- a/plat/renesas/rzg/platform.mk
+++ b/plat/renesas/rzg/platform.mk
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
+# Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-3-Clause
 #
@@ -32,6 +32,55 @@ else
       endif
       $(eval $(call add_define,RCAR_LSI_CUT))
     endif
+  else ifeq (${LSI},G2H)
+    RCAR_LSI:=${RZ_G2H}
+    ifndef LSI_CUT
+      # enable compatible function.
+      RCAR_LSI_CUT_COMPAT := 1
+      $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+    else
+      # disable compatible function.
+      ifeq (${LSI_CUT},30)
+        RCAR_LSI_CUT:=20
+      else
+        $(error "Error: ${LSI_CUT} is not supported.")
+      endif
+      $(eval $(call add_define,RCAR_LSI_CUT))
+    endif
+  else ifeq (${LSI},G2N)
+    RCAR_LSI:=${RZ_G2N}
+    ifndef LSI_CUT
+      # enable compatible function.
+      RCAR_LSI_CUT_COMPAT := 1
+      $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+    else
+      # disable compatible function.
+      ifeq (${LSI_CUT},10)
+        RCAR_LSI_CUT:=0
+      else ifeq (${LSI_CUT},11)
+        RCAR_LSI_CUT:=1
+      else
+        $(error "Error: ${LSI_CUT} is not supported.")
+      endif
+      $(eval $(call add_define,RCAR_LSI_CUT))
+    endif
+  else ifeq (${LSI},G2E)
+    RCAR_LSI:=${RZ_G2E}
+    ifndef LSI_CUT
+      # enable compatible function.
+      RCAR_LSI_CUT_COMPAT := 1
+      $(eval $(call add_define,RCAR_LSI_CUT_COMPAT))
+    else
+      # disable compatible function.
+      ifeq (${LSI_CUT},10)
+        RCAR_LSI_CUT:=0
+      else ifeq (${LSI_CUT},11)
+        RCAR_LSI_CUT:=1
+      else
+        $(error "Error: ${LSI_CUT} is not supported.")
+      endif
+      $(eval $(call add_define,RCAR_LSI_CUT))
+    endif
   else
     $(error "Error: ${LSI} is not supported.")
   endif
@@ -168,12 +217,15 @@ RCAR_SYSTEM_RESET_KEEPON_DDR := 0
 endif
 $(eval $(call add_define,RCAR_SYSTEM_RESET_KEEPON_DDR))
 
-include drivers/renesas/rzg/ddr/ddr.mk
+RZG_SOC :=1
+$(eval $(call add_define,RZG_SOC))
+
+include drivers/renesas/common/ddr/ddr.mk
 include drivers/renesas/rzg/qos/qos.mk
 include drivers/renesas/rzg/pfc/pfc.mk
 include lib/libfdt/libfdt.mk
 
-PLAT_INCLUDES	+=	-Idrivers/renesas/rzg/ddr		\
+PLAT_INCLUDES	+=	-Idrivers/renesas/common/ddr		\
 			-Idrivers/renesas/rzg/qos		\
 			-Idrivers/renesas/rzg/board		\
 			-Idrivers/renesas/common		\