diff options
| -rw-r--r-- | include/arch/aarch64/arch.h | 8 | ||||
| -rw-r--r-- | include/arch/aarch64/el3_common_macros.S | 17 | ||||
| -rw-r--r-- | lib/el3_runtime/aarch64/context.S | 18 |
3 files changed, 29 insertions, 14 deletions
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h index b86a13ed3..9ef9c2689 100644 --- a/include/arch/aarch64/arch.h +++ b/include/arch/aarch64/arch.h @@ -434,8 +434,16 @@ #define SCR_RESET_VAL SCR_RES1_BITS /* MDCR_EL3 definitions */ +#define MDCR_EnPMSN_BIT (ULL(1) << 36) +#define MDCR_MPMX_BIT (ULL(1) << 35) +#define MDCR_MCCD_BIT (ULL(1) << 34) #define MDCR_MTPME_BIT (ULL(1) << 28) +#define MDCR_TDCC_BIT (ULL(1) << 27) #define MDCR_SCCD_BIT (ULL(1) << 23) +#define MDCR_EPMAD_BIT (ULL(1) << 21) +#define MDCR_EDAD_BIT (ULL(1) << 20) +#define MDCR_TTRF_BIT (ULL(1) << 19) +#define MDCR_STE_BIT (ULL(1) << 18) #define MDCR_SPME_BIT (ULL(1) << 17) #define MDCR_SDD_BIT (ULL(1) << 16) #define MDCR_SPD32(x) ((x) << 14) diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index f75998351..b610b37bd 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -113,8 +113,13 @@ * * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is * prohibited in Secure state. This bit is RES0 in versions of the - * architecture earlier than ARMv8.5, setting it to 1 doesn't have any - * effect on them. + * architecture with FEAT_PMUv3p5 not implemented, setting it to 1 + * doesn't have any effect on them. + * + * MDCR_EL3.MCCD: Set to one so that cycle counting by PMCCNTR_EL0 is + * prohibited in EL3. This bit is RES0 in versions of the + * architecture with FEAT_PMUv3p7 not implemented, setting it to 1 + * doesn't have any effect on them. * * MDCR_EL3.SPME: Set to zero so that event counting by the programmable * counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If ARMv8.2 @@ -124,9 +129,9 @@ * --------------------------------------------------------------------- */ mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \ - MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) & \ - ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | MDCR_TDA_BIT | \ - MDCR_TPM_BIT)) + MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT | \ + MDCR_MCCD_BIT) & ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | \ + MDCR_TDA_BIT | MDCR_TPM_BIT)) msr mdcr_el3, x0 diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S index 7daf30da1..0ec9ffd5d 100644 --- a/lib/el3_runtime/aarch64/context.S +++ b/lib/el3_runtime/aarch64/context.S @@ -697,13 +697,14 @@ func save_gp_pmcr_pauth_regs str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] /* ---------------------------------------------------------- - * Check if earlier initialization MDCR_EL3.SCCD to 1 failed, - * meaning that ARMv8-PMU is not implemented and PMCR_EL0 - * should be saved in non-secure context. + * Check if earlier initialization MDCR_EL3.SCCD/MCCD to 1 + * failed, meaning that FEAT_PMUv3p5/7 is not implemented and + * PMCR_EL0 should be saved in non-secure context. * ---------------------------------------------------------- */ + mov_imm x10, (MDCR_SCCD_BIT | MDCR_MCCD_BIT) mrs x9, mdcr_el3 - tst x9, #MDCR_SCCD_BIT + tst x9, x10 bne 1f /* Secure Cycle Counter is not disabled */ @@ -792,13 +793,14 @@ func restore_gp_pmcr_pauth_regs /* ---------------------------------------------------------- * Back to Non-secure state. - * Check if earlier initialization MDCR_EL3.SCCD to 1 failed, - * meaning that ARMv8-PMU is not implemented and PMCR_EL0 - * should be restored from non-secure context. + * Check if earlier initialization MDCR_EL3.SCCD/MCCD to 1 + * failed, meaning that FEAT_PMUv3p5/7 is not implemented and + * PMCR_EL0 should be restored from non-secure context. * ---------------------------------------------------------- */ + mov_imm x1, (MDCR_SCCD_BIT | MDCR_MCCD_BIT) mrs x0, mdcr_el3 - tst x0, #MDCR_SCCD_BIT + tst x0, x1 bne 2f ldr x0, [sp, #CTX_EL3STATE_OFFSET + CTX_PMCR_EL0] msr pmcr_el0, x0 |