diff options
| -rw-r--r-- | bl2/aarch32/bl2_entrypoint.S | 8 | ||||
| -rw-r--r-- | bl2u/aarch32/bl2u_entrypoint.S | 5 | ||||
| -rw-r--r-- | bl2u/aarch64/bl2u_entrypoint.S | 9 | ||||
| -rw-r--r-- | bl32/tsp/aarch64/tsp_entrypoint.S | 16 | ||||
| -rw-r--r-- | include/arch/aarch32/el3_common_macros.S | 11 |
5 files changed, 32 insertions, 17 deletions
diff --git a/bl2/aarch32/bl2_entrypoint.S b/bl2/aarch32/bl2_entrypoint.S index 102fd2f51..6e8e2c1e1 100644 --- a/bl2/aarch32/bl2_entrypoint.S +++ b/bl2/aarch32/bl2_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -80,12 +80,14 @@ func bl2_entrypoint * --------------------------------------------- */ ldr r0, =__BSS_START__ - ldr r1, =__BSS_SIZE__ + ldr r1, =__BSS_END__ + sub r1, r1, r0 bl zeromem #if USE_COHERENT_MEM ldr r0, =__COHERENT_RAM_START__ - ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__ + ldr r1, =__COHERENT_RAM_END_UNALIGNED__ + sub r1, r1, r0 bl zeromem #endif diff --git a/bl2u/aarch32/bl2u_entrypoint.S b/bl2u/aarch32/bl2u_entrypoint.S index 6391f537c..e4dd03dec 100644 --- a/bl2u/aarch32/bl2u_entrypoint.S +++ b/bl2u/aarch32/bl2u_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -79,7 +79,8 @@ func bl2u_entrypoint * --------------------------------------------- */ ldr r0, =__BSS_START__ - ldr r1, =__BSS_SIZE__ + ldr r1, =__BSS_END__ + sub r1, r1, r0 bl zeromem /* -------------------------------------------- diff --git a/bl2u/aarch64/bl2u_entrypoint.S b/bl2u/aarch64/bl2u_entrypoint.S index 3e37b44f7..15978b6d4 100644 --- a/bl2u/aarch64/bl2u_entrypoint.S +++ b/bl2u/aarch64/bl2u_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -69,8 +69,11 @@ func bl2u_entrypoint * - the coherent memory section. * --------------------------------------------- */ - ldr x0, =__BSS_START__ - ldr x1, =__BSS_SIZE__ + adrp x0, __BSS_START__ + add x0, x0, :lo12:__BSS_START__ + adrp x1, __BSS_END__ + add x1, x1, :lo12:__BSS_END__ + sub x1, x1, x0 bl zeromem /* -------------------------------------------- diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index a007bab30..795c5865e 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -114,13 +114,19 @@ func tsp_entrypoint _align=3 * - the coherent memory section. * --------------------------------------------- */ - ldr x0, =__BSS_START__ - ldr x1, =__BSS_SIZE__ + adrp x0, __BSS_START__ + add x0, x0, :lo12:__BSS_START__ + adrp x1, __BSS_END__ + add x1, x1, :lo12:__BSS_END__ + sub x1, x1, x0 bl zeromem #if USE_COHERENT_MEM - ldr x0, =__COHERENT_RAM_START__ - ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ + adrp x0, __COHERENT_RAM_START__ + add x0, x0, :lo12:__COHERENT_RAM_START__ + adrp x1, __COHERENT_RAM_END_UNALIGNED__ + add x1, x1, :lo12:__COHERENT_RAM_END_UNALIGNED__ + sub x1, x1, x0 bl zeromem #endif diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S index 580dd95b7..6caebf827 100644 --- a/include/arch/aarch32/el3_common_macros.S +++ b/include/arch/aarch32/el3_common_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -339,12 +339,14 @@ */ mov r7, r12 ldr r0, =__BSS_START__ - ldr r1, =__BSS_SIZE__ + ldr r1, =__BSS_END__ + sub r1, r1, r0 bl zeromem #if USE_COHERENT_MEM ldr r0, =__COHERENT_RAM_START__ - ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__ + ldr r1, =__COHERENT_RAM_END_UNALIGNED__ + sub r1, r1, r0 bl zeromem #endif @@ -358,7 +360,8 @@ */ ldr r0, =__DATA_RAM_START__ ldr r1, =__DATA_ROM_START__ - ldr r2, =__DATA_SIZE__ + ldr r2, =__DATA_RAM_END__ + sub r2, r2, r0 bl memcpy4 #endif .endif /* _init_c_runtime */ |