diff options
Diffstat (limited to 'lib/cpus')
| -rw-r--r-- | lib/cpus/aarch64/cortex_a710.S | 72 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_a78.S | 77 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_hayes.S | 77 | ||||
| -rw-r--r-- | lib/cpus/aarch64/cortex_hunter.S | 77 | ||||
| -rw-r--r-- | lib/cpus/aarch64/neoverse_demeter.S (renamed from lib/cpus/aarch64/cortex_demeter.S) | 46 | ||||
| -rw-r--r-- | lib/cpus/aarch64/neoverse_n2.S | 190 | ||||
| -rw-r--r-- | lib/cpus/aarch64/neoverse_v1.S | 78 | ||||
| -rw-r--r-- | lib/cpus/cpu-ops.mk | 126 | ||||
| -rw-r--r-- | lib/cpus/errata_report.c | 4 |
9 files changed, 697 insertions, 50 deletions
diff --git a/lib/cpus/aarch64/cortex_a710.S b/lib/cpus/aarch64/cortex_a710.S index 75b7647bd..7d7fbd888 100644 --- a/lib/cpus/aarch64/cortex_a710.S +++ b/lib/cpus/aarch64/cortex_a710.S @@ -160,6 +160,62 @@ func check_errata_2017096 b cpu_rev_var_ls endfunc check_errata_2017096 + +/* --------------------------------------------------------------------- + * Errata Workaround for Cortex-A710 Erratum 2083908. + * This applies to revision r2p0 of Cortex-A710 and is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * --------------------------------------------------------------------- + */ +func errata_a710_2083908_wa + /* Compare x0 against revision r2p0 */ + mov x17, x30 + bl check_errata_2083908 + cbz x0, 1f + mrs x1, CORTEX_A710_CPUACTLR5_EL1 + orr x1, x1, CORTEX_A710_CPUACTLR5_EL1_BIT_13 + msr CORTEX_A710_CPUACTLR5_EL1, x1 +1: + ret x17 +endfunc errata_a710_2083908_wa + +func check_errata_2083908 + /* Applies to r2p0 */ + mov x1, #CPU_REV(2, 0) + mov x2, #CPU_REV(2, 0) + b cpu_rev_var_range +endfunc check_errata_2083908 + +/* --------------------------------------------------------------------- + * Errata Workaround for Cortex-A710 Erratum 2058056. + * This applies to revisions r0p0, r1p0 and r2p0 of Cortex-A710 and is still + * open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * --------------------------------------------------------------------- + */ +func errata_a710_2058056_wa + /* Compare x0 against revision r2p0 */ + mov x17, x30 + bl check_errata_2058056 + cbz x0, 1f + mrs x1, CORTEX_A710_CPUECTLR2_EL1 + mov x0, #CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV + bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH + msr CORTEX_A710_CPUECTLR2_EL1, x1 +1: + ret x17 +endfunc errata_a710_2058056_wa + +func check_errata_2058056 + /* Applies to r0p0, r1p0 and r2p0 */ + mov x1, #0x20 + b cpu_rev_var_ls +endfunc check_errata_2058056 + /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- @@ -194,6 +250,8 @@ func cortex_a710_errata_report report_errata ERRATA_A710_2081180, cortex_a710, 2081180 report_errata ERRATA_A710_2055002, cortex_a710, 2055002 report_errata ERRATA_A710_2017096, cortex_a710, 2017096 + report_errata ERRATA_A710_2083908, cortex_a710, 2083908 + report_errata ERRATA_A710_2058056, cortex_a710, 2058056 ldp x8, x30, [sp], #16 ret @@ -225,8 +283,18 @@ func cortex_a710_reset_func #endif #if ERRATA_A710_2017096 - mov x0, x18 - bl errata_a710_2017096_wa + mov x0, x18 + bl errata_a710_2017096_wa +#endif + +#if ERRATA_A710_2083908 + mov x0, x18 + bl errata_a710_2083908_wa +#endif + +#if ERRATA_A710_2058056 + mov x0, x18 + bl errata_a710_2058056_wa #endif isb ret x19 diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S index 3a74571f0..a1288bab1 100644 --- a/lib/cpus/aarch64/cortex_a78.S +++ b/lib/cpus/aarch64/cortex_a78.S @@ -198,6 +198,71 @@ func check_errata_1952683 b cpu_rev_var_ls endfunc check_errata_1952683 +/* -------------------------------------------------- + * Errata Workaround for Cortex A78 Errata 2132060. + * This applies to revisions r0p0, r1p0, r1p1, and r1p2. + * It is still open. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * -------------------------------------------------- + */ +func errata_a78_2132060_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2132060 + cbz x0, 1f + + /* Apply the workaround. */ + mrs x1, CORTEX_A78_CPUECTLR_EL1 + mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV + bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH + msr CORTEX_A78_CPUECTLR_EL1, x1 +1: + ret x17 +endfunc errata_a78_2132060_wa + +func check_errata_2132060 + /* Applies to r0p0, r0p1, r1p1, and r1p2 */ + mov x1, #0x12 + b cpu_rev_var_ls +endfunc check_errata_2132060 + +/* -------------------------------------------------------------------- + * Errata Workaround for A78 Erratum 2242635. + * This applies to revisions r1p0, r1p1, and r1p2 of the Cortex A78 + * processor and is still open. + * The issue also exists in r0p0 but there is no fix in that revision. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------------------------- + */ +func errata_a78_2242635_wa + /* Compare x0 against revisions r1p0 - r1p2 */ + mov x17, x30 + bl check_errata_2242635 + cbz x0, 1f + + ldr x0, =0x5 + msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ + ldr x0, =0x10F600E000 + msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ + ldr x0, =0x10FF80E000 + msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ + ldr x0, =0x80000000003FF + msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ + + isb +1: + ret x17 +endfunc errata_a78_2242635_wa + +func check_errata_2242635 + /* Applies to revisions r1p0 through r1p2. */ + mov x1, #CPU_REV(1, 0) + mov x2, #CPU_REV(1, 2) + b cpu_rev_var_range +endfunc check_errata_2242635 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A78 * ------------------------------------------------- @@ -232,6 +297,16 @@ func cortex_a78_reset_func bl errata_a78_1952683_wa #endif +#if ERRATA_A78_2132060 + mov x0, x18 + bl errata_a78_2132060_wa +#endif + +#if ERRATA_A78_2242635 + mov x0, x18 + bl errata_a78_2242635_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 @@ -291,6 +366,8 @@ func cortex_a78_errata_report report_errata ERRATA_A78_1951500, cortex_a78, 1951500 report_errata ERRATA_A78_1821534, cortex_a78, 1821534 report_errata ERRATA_A78_1952683, cortex_a78, 1952683 + report_errata ERRATA_A78_2132060, cortex_a78, 2132060 + report_errata ERRATA_A78_2242635, cortex_a78, 2242635 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/aarch64/cortex_hayes.S b/lib/cpus/aarch64/cortex_hayes.S new file mode 100644 index 000000000..445a69187 --- /dev/null +++ b/lib/cpus/aarch64/cortex_hayes.S @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <common/bl_common.h> +#include <cortex_hayes.h> +#include <cpu_macros.S> +#include <plat_macros.S> + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex Hayes must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex Hayes supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_hayes_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + mrs x0, CORTEX_HAYES_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_HAYES_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_HAYES_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_hayes_core_pwr_dwn + + /* + * Errata printing function for Cortex Hayes. Must follow AAPCS. + */ +#if REPORT_ERRATA +func cortex_hayes_errata_report + ret +endfunc cortex_hayes_errata_report +#endif + +func cortex_hayes_reset_func + /* Disable speculative loads */ + msr SSBS, xzr + isb + ret +endfunc cortex_hayes_reset_func + + /* --------------------------------------------- + * This function provides Cortex Hayes specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_hayes_regs, "aS" +cortex_hayes_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_hayes_cpu_reg_dump + adr x6, cortex_hayes_regs + mrs x8, CORTEX_HAYES_CPUECTLR_EL1 + ret +endfunc cortex_hayes_cpu_reg_dump + +declare_cpu_ops cortex_hayes, CORTEX_HAYES_MIDR, \ + cortex_hayes_reset_func, \ + cortex_hayes_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_hunter.S b/lib/cpus/aarch64/cortex_hunter.S new file mode 100644 index 000000000..2ab429615 --- /dev/null +++ b/lib/cpus/aarch64/cortex_hunter.S @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2021, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <common/bl_common.h> +#include <cortex_hunter.h> +#include <cpu_macros.S> +#include <plat_macros.S> + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "Cortex Hunter must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + +/* 64-bit only core */ +#if CTX_INCLUDE_AARCH32_REGS == 1 +#error "Cortex Hunter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#endif + +func cortex_hunter_reset_func + /* Disable speculative loads */ + msr SSBS, xzr + isb + ret +endfunc cortex_hunter_reset_func + + /* ---------------------------------------------------- + * HW will do the cache maintenance while powering down + * ---------------------------------------------------- + */ +func cortex_hunter_core_pwr_dwn + /* --------------------------------------------------- + * Enable CPU power down bit in power control register + * --------------------------------------------------- + */ + mrs x0, CORTEX_HUNTER_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_HUNTER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr CORTEX_HUNTER_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_hunter_core_pwr_dwn + +#if REPORT_ERRATA +/* + * Errata printing function for Cortex Hunter. Must follow AAPCS. + */ +func cortex_hunter_errata_report + ret +endfunc cortex_hunter_errata_report +#endif + + /* --------------------------------------------- + * This function provides Cortex Hunter-specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * --------------------------------------------- + */ +.section .rodata.cortex_hunter_regs, "aS" +cortex_hunter_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_hunter_cpu_reg_dump + adr x6, cortex_hunter_regs + mrs x8, CORTEX_HUNTER_CPUECTLR_EL1 + ret +endfunc cortex_hunter_cpu_reg_dump + +declare_cpu_ops cortex_hunter, CORTEX_HUNTER_MIDR, \ + cortex_hunter_reset_func, \ + cortex_hunter_core_pwr_dwn diff --git a/lib/cpus/aarch64/cortex_demeter.S b/lib/cpus/aarch64/neoverse_demeter.S index 9ad8b86fd..f43c18b6b 100644 --- a/lib/cpus/aarch64/cortex_demeter.S +++ b/lib/cpus/aarch64/neoverse_demeter.S @@ -7,54 +7,54 @@ #include <arch.h> #include <asm_macros.S> #include <common/bl_common.h> -#include <cortex_demeter.h> +#include <neoverse_demeter.h> #include <cpu_macros.S> #include <plat_macros.S> /* Hardware handled coherency */ #if HW_ASSISTED_COHERENCY == 0 -#error "Cortex Demeter must be compiled with HW_ASSISTED_COHERENCY enabled" +#error "Neoverse Demeter must be compiled with HW_ASSISTED_COHERENCY enabled" #endif /* 64-bit only core */ #if CTX_INCLUDE_AARCH32_REGS == 1 -#error "Cortex Demeter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" +#error "Neoverse Demeter supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- */ -func cortex_demeter_core_pwr_dwn +func neoverse_demeter_core_pwr_dwn /* --------------------------------------------------- * Enable CPU power down bit in power control register * --------------------------------------------------- */ - mrs x0, CORTEX_DEMETER_CPUPWRCTLR_EL1 - orr x0, x0, #CORTEX_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT - msr CORTEX_DEMETER_CPUPWRCTLR_EL1, x0 + mrs x0, NEOVERSE_DEMETER_CPUPWRCTLR_EL1 + orr x0, x0, #NEOVERSE_DEMETER_CPUPWRCTLR_EL1_CORE_PWRDN_BIT + msr NEOVERSE_DEMETER_CPUPWRCTLR_EL1, x0 isb ret -endfunc cortex_demeter_core_pwr_dwn +endfunc neoverse_demeter_core_pwr_dwn #if REPORT_ERRATA /* - * Errata printing function for Cortex Demeter. Must follow AAPCS. + * Errata printing function for Neoverse Demeter. Must follow AAPCS. */ -func cortex_demeter_errata_report +func neoverse_demeter_errata_report ret -endfunc cortex_demeter_errata_report +endfunc neoverse_demeter_errata_report #endif -func cortex_demeter_reset_func +func neoverse_demeter_reset_func /* Disable speculative loads */ msr SSBS, xzr isb ret -endfunc cortex_demeter_reset_func +endfunc neoverse_demeter_reset_func /* --------------------------------------------- - * This function provides Cortex Demeter- + * This function provides Neoverse Demeter- * specific register information for crash * reporting. It needs to return with x6 * pointing to a list of register names in ascii @@ -62,16 +62,16 @@ endfunc cortex_demeter_reset_func * reported. * --------------------------------------------- */ -.section .rodata.cortex_demeter_regs, "aS" -cortex_demeter_regs: /* The ascii list of register names to be reported */ +.section .rodata.neoverse_demeter_regs, "aS" +neoverse_demeter_regs: /* The ascii list of register names to be reported */ .asciz "cpuectlr_el1", "" -func cortex_demeter_cpu_reg_dump - adr x6, cortex_demeter_regs - mrs x8, CORTEX_DEMETER_CPUECTLR_EL1 +func neoverse_demeter_cpu_reg_dump + adr x6, neoverse_demeter_regs + mrs x8, NEOVERSE_DEMETER_CPUECTLR_EL1 ret -endfunc cortex_demeter_cpu_reg_dump +endfunc neoverse_demeter_cpu_reg_dump -declare_cpu_ops cortex_demeter, CORTEX_DEMETER_MIDR, \ - cortex_demeter_reset_func, \ - cortex_demeter_core_pwr_dwn +declare_cpu_ops neoverse_demeter, NEOVERSE_DEMETER_MIDR, \ + neoverse_demeter_reset_func, \ + neoverse_demeter_core_pwr_dwn diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S index 9e7bbf7e6..621aded7c 100644 --- a/lib/cpus/aarch64/neoverse_n2.S +++ b/lib/cpus/aarch64/neoverse_n2.S @@ -183,6 +183,156 @@ func check_errata_2138956 b cpu_rev_var_ls endfunc check_errata_2138956 +/* -------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2242415. + * This applies to revision r0p0 of Neoverse N2. it is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * -------------------------------------------------- + */ +func errata_n2_2242415_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2242415 + cbz x0, 1f + + /* Apply instruction patching sequence */ + mrs x1, NEOVERSE_N2_CPUACTLR_EL1 + orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 + msr NEOVERSE_N2_CPUACTLR_EL1, x1 +1: + ret x17 +endfunc errata_n2_2242415_wa + +func check_errata_2242415 + /* Applies to r0p0 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2242415 + +/* -------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2138953. + * This applies to revision r0p0 of Neoverse N2. it is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * -------------------------------------------------- + */ +func errata_n2_2138953_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2138953 + cbz x0, 1f + + /* Apply instruction patching sequence */ + mrs x1, NEOVERSE_N2_CPUECTLR2_EL1 + mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV + bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH + msr NEOVERSE_N2_CPUECTLR2_EL1, x1 +1: + ret x17 +endfunc errata_n2_2138953_wa + +func check_errata_2138953 + /* Applies to r0p0 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2138953 + +/* -------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2138958. + * This applies to revision r0p0 of Neoverse N2. it is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * -------------------------------------------------- + */ +func errata_n2_2138958_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2138958 + cbz x0, 1f + + /* Apply instruction patching sequence */ + mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 + orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 + msr NEOVERSE_N2_CPUACTLR5_EL1, x1 +1: + ret x17 +endfunc errata_n2_2138958_wa + +func check_errata_2138958 + /* Applies to r0p0 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2138958 + +/* -------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2242400. + * This applies to revision r0p0 of Neoverse N2. it is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * -------------------------------------------------- + */ +func errata_n2_2242400_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2242400 + cbz x0, 1f + + /* Apply instruction patching sequence */ + mrs x1, NEOVERSE_N2_CPUACTLR5_EL1 + orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 + msr NEOVERSE_N2_CPUACTLR5_EL1, x1 + ldr x0, =0x2 + msr S3_6_c15_c8_0, x0 + ldr x0, =0x10F600E000 + msr S3_6_c15_c8_2, x0 + ldr x0, =0x10FF80E000 + msr S3_6_c15_c8_3, x0 + ldr x0, =0x80000000003FF + msr S3_6_c15_c8_1, x0 + isb +1: + ret x17 +endfunc errata_n2_2242400_wa + +func check_errata_2242400 + /* Applies to r0p0 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2242400 + +/* -------------------------------------------------- + * Errata Workaround for Neoverse N2 Erratum 2280757. + * This applies to revision r0p0 of Neoverse N2. it is still open. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * -------------------------------------------------- + */ +func errata_n2_2280757_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2280757 + cbz x0, 1f + + /* Apply instruction patching sequence */ + mrs x1, NEOVERSE_N2_CPUACTLR_EL1 + orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22 + msr NEOVERSE_N2_CPUACTLR_EL1, x1 +1: + ret x17 +endfunc errata_n2_2280757_wa + +func check_errata_2280757 + /* Applies to r0p0 */ + mov x1, #0x00 + b cpu_rev_var_ls +endfunc check_errata_2280757 + /* ------------------------------------------- * The CPU Ops reset function for Neoverse N2. * ------------------------------------------- @@ -209,13 +359,13 @@ func neoverse_n2_reset_func #endif #if ERRATA_N2_2025414 - mov x0, x18 - bl errata_n2_2025414_wa + mov x0, x18 + bl errata_n2_2025414_wa #endif #if ERRATA_N2_2189731 - mov x0, x18 - bl errata_n2_2189731_wa + mov x0, x18 + bl errata_n2_2189731_wa #endif @@ -224,6 +374,31 @@ func neoverse_n2_reset_func bl errata_n2_2138956_wa #endif +#if ERRATA_N2_2138953 + mov x0, x18 + bl errata_n2_2138953_wa +#endif + +#if ERRATA_N2_2242415 + mov x0, x18 + bl errata_n2_2242415_wa +#endif + +#if ERRATA_N2_2138958 + mov x0, x18 + bl errata_n2_2138958_wa +#endif + +#if ERRATA_N2_2242400 + mov x0, x18 + bl errata_n2_2242400_wa +#endif + +#if ERRATA_N2_2280757 + mov x0, x18 + bl errata_n2_2280757_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, cptr_el3 @@ -287,8 +462,13 @@ func neoverse_n2_errata_report report_errata ERRATA_N2_2002655, neoverse_n2, 2002655 report_errata ERRATA_N2_2067956, neoverse_n2, 2067956 report_errata ERRATA_N2_2025414, neoverse_n2, 2025414 - report_errata ERRATA_N2_2189731, neoverse_n2, 2189731 + report_errata ERRATA_N2_2189731, neoverse_n2, 2189731 report_errata ERRATA_N2_2138956, neoverse_n2, 2138956 + report_errata ERRATA_N2_2138953, neoverse_n2, 2138953 + report_errata ERRATA_N2_2242415, neoverse_n2, 2242415 + report_errata ERRATA_N2_2138958, neoverse_n2, 2138958 + report_errata ERRATA_N2_2242400, neoverse_n2, 2242400 + report_errata ERRATA_N2_2280757, neoverse_n2, 2280757 ldp x8, x30, [sp], #16 ret diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S index 0bcf52a78..62a7a30cd 100644 --- a/lib/cpus/aarch64/neoverse_v1.S +++ b/lib/cpus/aarch64/neoverse_v1.S @@ -259,6 +259,72 @@ func check_errata_2139242 b cpu_rev_var_ls endfunc check_errata_2139242 + /* -------------------------------------------------- + * Errata Workaround for Neoverse V1 Errata #2108267. + * This applies to revisions r0p0, r1p0, and r1p1, it + * is still open. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * -------------------------------------------------- + */ +func errata_neoverse_v1_2108267_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_2108267 + cbz x0, 1f + + /* Apply the workaround. */ + mrs x1, NEOVERSE_V1_CPUECTLR_EL1 + mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV + bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH + msr NEOVERSE_V1_CPUECTLR_EL1, x1 +1: + ret x17 +endfunc errata_neoverse_v1_2108267_wa + +func check_errata_2108267 + /* Applies to r0p0, r1p0, r1p1 */ + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_2108267 + + /* -------------------------------------------------- + * Errata Workaround for Neoverse V1 Errata #2216392. + * This applies to revisions r1p0 and r1p1 and is + * still open. + * This issue is also present in r0p0 but there is no + * workaround in that revision. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_neoverse_v1_2216392_wa + /* Check workaround compatibility. */ + mov x17, x30 + bl check_errata_2216392 + cbz x0, 1f + + ldr x0, =0x5 + msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */ + ldr x0, =0x10F600E000 + msr S3_6_c15_c8_2, x0 /* CPUPOR_EL3 */ + ldr x0, =0x10FF80E000 + msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */ + ldr x0, =0x80000000003FF + msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */ + + isb +1: + ret x17 +endfunc errata_neoverse_v1_2216392_wa + +func check_errata_2216392 + /* Applies to revisions r1p0 and r1p1. */ + mov x1, #CPU_REV(1, 0) + mov x2, #CPU_REV(1, 1) + b cpu_rev_var_range +endfunc check_errata_2216392 + /* --------------------------------------------- * HW will do the cache maintenance while powering down * --------------------------------------------- @@ -296,6 +362,8 @@ func neoverse_v1_errata_report report_errata ERRATA_V1_1940577, neoverse_v1, 1940577 report_errata ERRATA_V1_1966096, neoverse_v1, 1966096 report_errata ERRATA_V1_2139242, neoverse_v1, 2139242 + report_errata ERRATA_V1_2108267, neoverse_v1, 2108267 + report_errata ERRATA_V1_2216392, neoverse_v1, 2216392 ldp x8, x30, [sp], #16 ret @@ -344,6 +412,16 @@ func neoverse_v1_reset_func bl errata_neoverse_v1_2139242_wa #endif +#if ERRATA_V1_2108267 + mov x0, x18 + bl errata_neoverse_v1_2108267_wa +#endif + +#if ERRATA_V1_2216392 + mov x0, x18 + bl errata_neoverse_v1_2216392_wa +#endif + ret x19 endfunc neoverse_v1_reset_func diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 6103a5a7b..a5b8aae29 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -311,6 +311,23 @@ ERRATA_A78_1941498 ?=0 # well but there is no workaround for that revision. ERRATA_A78_1951500 ?=0 +# Flag to apply erratum 1821534 workaround during reset. This erratum applies +# to revisions r0p0 and r1p0 of the A78 cpu. +ERRATA_A78_1821534 ?=0 + +# Flag to apply erratum 1952683 workaround during reset. This erratum applies +# to revision r0p0 of the A78 cpu and was fixed in the revision r1p0. +ERRATA_A78_1952683 ?=0 + +# Flag to apply erratum 2132060 workaround during reset. This erratum applies +# to revisions r0p0, r1p0, r1p1, and r1p2 of the A78 cpu. It is still open. +ERRATA_A78_2132060 ?=0 + +# Flag to apply erratum 2242635 workaround during reset. This erratum applies +# to revisions r1p0, r1p1, and r1p2 of the A78 cpu and is open. The issue is +# present in r0p0 as well but there is no workaround for that revision. +ERRATA_A78_2242635 ?=0 + # Flag to apply erratum 1941500 workaround during reset. This erratum applies # to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open. ERRATA_A78_AE_1941500 ?=0 @@ -319,14 +336,6 @@ ERRATA_A78_AE_1941500 ?=0 # to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open. ERRATA_A78_AE_1951502 ?=0 -# Flag to apply erratum 1821534 workaround during reset. This erratum applies -# to revisions r0p0 and r1p0 of the A78 cpu. -ERRATA_A78_1821534 ?=0 - -# Flag to apply erratum 1952683 workaround during reset. This erratum applies -# to revision r0p0 of the A78 cpu and was fixed in the revision r1p0. -ERRATA_A78_1952683 ?=0 - # Flag to apply T32 CLREX workaround during reset. This erratum applies # only to r0p0 and r1p0 of the Neoverse N1 cpu. ERRATA_N1_1043202 ?=0 @@ -411,11 +420,20 @@ ERRATA_V1_1940577 ?=0 # Flag to apply erratum 1966096 workaround during reset. This erratum applies # to revisions r1p0 and r1p1 of the Neoverse V1 CPU and is open. This issue # exists in r0p0 as well but there is no workaround for that revision. -ERRATA_V1_1966096 ?=0 +ERRATA_V1_1966096 ?=0 # Flag to apply erratum 2139242 workaround during reset. This erratum applies # to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open. -ERRATA_V1_2139242 ?=0 +ERRATA_V1_2139242 ?=0 + +# Flag to apply erratum 2108267 workaround during reset. This erratum applies +# to revisions r0p0, r1p0, and r1p1 of the Neoverse V1 cpu and is still open. +ERRATA_V1_2108267 ?=0 + +# Flag to apply erratum 2216392 workaround during reset. This erratum applies +# to revisions r1p0 and r1p1 of the Neoverse V1 cpu and is still open. This +# issue exists in r0p0 as well but there is no workaround for that revision. +ERRATA_V1_2216392 ?=0 # Flag to apply erratum 1987031 workaround during reset. This erratum applies # to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. @@ -425,6 +443,14 @@ ERRATA_A710_1987031 ?=0 # to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. ERRATA_A710_2081180 ?=0 +# Flag to apply erratum 2083908 workaround during reset. This erratum applies +# to revision r2p0 of the Cortex-A710 cpu and is still open. +ERRATA_A710_2083908 ?=0 + +# Flag to apply erratum 2058056 workaround during reset. This erratum applies +# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open. +ERRATA_A710_2058056 ?=0 + # Flag to apply erratum 2067956 workaround during reset. This erratum applies # to revision r0p0 of the Neoverse N2 cpu and is still open. ERRATA_N2_2067956 ?=0 @@ -441,6 +467,26 @@ ERRATA_N2_2189731 ?=0 # to revision r0p0 of the Neoverse N2 cpu and is still open. ERRATA_N2_2138956 ?=0 +# Flag to apply erratum 2138953 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu and is still open. +ERRATA_N2_2138953 ?=0 + +# Flag to apply erratum 2242415 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu and is still open. +ERRATA_N2_2242415 ?=0 + +# Flag to apply erratum 2138958 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu and is still open. +ERRATA_N2_2138958 ?=0 + +# Flag to apply erratum 2242400 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu and is still open. +ERRATA_N2_2242400 ?=0 + +# Flag to apply erratum 2280757 workaround during reset. This erratum applies +# to revision r0p0 of the Neoverse N2 cpu and is still open. +ERRATA_N2_2280757 ?=0 + # Flag to apply erratum 2055002 workaround during reset. This erratum applies # to revision r1p0, r2p0 of the Cortex-A710 cpu and is still open. ERRATA_A710_2055002 ?=0 @@ -694,14 +740,6 @@ $(eval $(call add_define,ERRATA_A78_1941498)) $(eval $(call assert_boolean,ERRATA_A78_1951500)) $(eval $(call add_define,ERRATA_A78_1951500)) -# Process ERRATA_A78_AE_1941500 flag -$(eval $(call assert_boolean,ERRATA_A78_AE_1941500)) -$(eval $(call add_define,ERRATA_A78_AE_1941500)) - -# Process ERRATA_A78_AE_1951502 flag -$(eval $(call assert_boolean,ERRATA_A78_AE_1951502)) -$(eval $(call add_define,ERRATA_A78_AE_1951502)) - # Process ERRATA_A78_1821534 flag $(eval $(call assert_boolean,ERRATA_A78_1821534)) $(eval $(call add_define,ERRATA_A78_1821534)) @@ -710,6 +748,22 @@ $(eval $(call add_define,ERRATA_A78_1821534)) $(eval $(call assert_boolean,ERRATA_A78_1952683)) $(eval $(call add_define,ERRATA_A78_1952683)) +# Process ERRATA_A78_2132060 flag +$(eval $(call assert_boolean,ERRATA_A78_2132060)) +$(eval $(call add_define,ERRATA_A78_2132060)) + +# Process ERRATA_A78_2242635 flag +$(eval $(call assert_boolean,ERRATA_A78_2242635)) +$(eval $(call add_define,ERRATA_A78_2242635)) + +# Process ERRATA_A78_AE_1941500 flag +$(eval $(call assert_boolean,ERRATA_A78_AE_1941500)) +$(eval $(call add_define,ERRATA_A78_AE_1941500)) + +# Process ERRATA_A78_AE_1951502 flag +$(eval $(call assert_boolean,ERRATA_A78_AE_1951502)) +$(eval $(call add_define,ERRATA_A78_AE_1951502)) + # Process ERRATA_N1_1043202 flag $(eval $(call assert_boolean,ERRATA_N1_1043202)) $(eval $(call add_define,ERRATA_N1_1043202)) @@ -798,6 +852,14 @@ $(eval $(call add_define,ERRATA_V1_1966096)) $(eval $(call assert_boolean,ERRATA_V1_2139242)) $(eval $(call add_define,ERRATA_V1_2139242)) +# Process ERRATA_V1_2108267 flag +$(eval $(call assert_boolean,ERRATA_V1_2108267)) +$(eval $(call add_define,ERRATA_V1_2108267)) + +# Process ERRATA_V1_2216392 flag +$(eval $(call assert_boolean,ERRATA_V1_2216392)) +$(eval $(call add_define,ERRATA_V1_2216392)) + # Process ERRATA_A710_1987031 flag $(eval $(call assert_boolean,ERRATA_A710_1987031)) $(eval $(call add_define,ERRATA_A710_1987031)) @@ -806,6 +868,14 @@ $(eval $(call add_define,ERRATA_A710_1987031)) $(eval $(call assert_boolean,ERRATA_A710_2081180)) $(eval $(call add_define,ERRATA_A710_2081180)) +# Process ERRATA_A710_2083908 flag +$(eval $(call assert_boolean,ERRATA_A710_2083908)) +$(eval $(call add_define,ERRATA_A710_2083908)) + +# Process ERRATA_A710_2058056 flag +$(eval $(call assert_boolean,ERRATA_A710_2058056)) +$(eval $(call add_define,ERRATA_A710_2058056)) + # Process ERRATA_N2_2067956 flag $(eval $(call assert_boolean,ERRATA_N2_2067956)) $(eval $(call add_define,ERRATA_N2_2067956)) @@ -822,6 +892,26 @@ $(eval $(call add_define,ERRATA_N2_2189731)) $(eval $(call assert_boolean,ERRATA_N2_2138956)) $(eval $(call add_define,ERRATA_N2_2138956)) +# Process ERRATA_N2_2138953 flag +$(eval $(call assert_boolean,ERRATA_N2_2138953)) +$(eval $(call add_define,ERRATA_N2_2138953)) + +# Process ERRATA_N2_2242415 flag +$(eval $(call assert_boolean,ERRATA_N2_2242415)) +$(eval $(call add_define,ERRATA_N2_2242415)) + +# Process ERRATA_N2_2138958 flag +$(eval $(call assert_boolean,ERRATA_N2_2138958)) +$(eval $(call add_define,ERRATA_N2_2138958)) + +# Process ERRATA_N2_2242400 flag +$(eval $(call assert_boolean,ERRATA_N2_2242400)) +$(eval $(call add_define,ERRATA_N2_2242400)) + +# Process ERRATA_N2_2280757 flag +$(eval $(call assert_boolean,ERRATA_N2_2280757)) +$(eval $(call add_define,ERRATA_N2_2280757)) + # Process ERRATA_A710_2055002 flag $(eval $(call assert_boolean,ERRATA_A710_2055002)) $(eval $(call add_define,ERRATA_A710_2055002)) diff --git a/lib/cpus/errata_report.c b/lib/cpus/errata_report.c index 5d1e3c5cc..93b27444f 100644 --- a/lib/cpus/errata_report.c +++ b/lib/cpus/errata_report.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2021, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,7 +19,7 @@ # define BL_STRING "BL1" #elif defined(__aarch64__) && defined(IMAGE_BL31) # define BL_STRING "BL31" -#elif !defined(__arch64__) && defined(IMAGE_BL32) +#elif !defined(__aarch64__) && defined(IMAGE_BL32) # define BL_STRING "BL32" #elif defined(IMAGE_BL2) && BL2_AT_EL3 # define BL_STRING "BL2" |