diff options
Diffstat (limited to 'plat/arm/board/fvp')
-rw-r--r-- | plat/arm/board/fvp/fvp_bl1_setup.c | 3 | ||||
-rw-r--r-- | plat/arm/board/fvp/fvp_bl2_setup.c | 15 | ||||
-rw-r--r-- | plat/arm/board/fvp/fvp_bl2u_setup.c | 5 | ||||
-rw-r--r-- | plat/arm/board/fvp/fvp_bl31_setup.c | 5 | ||||
-rw-r--r-- | plat/arm/board/fvp/fvp_common.c | 50 | ||||
-rw-r--r-- | plat/arm/board/fvp/fvp_def.h | 8 | ||||
-rw-r--r-- | plat/arm/board/fvp/fvp_pm.c | 18 | ||||
-rw-r--r-- | plat/arm/board/fvp/fvp_private.h | 1 | ||||
-rw-r--r-- | plat/arm/board/fvp/fvp_topology.c | 5 | ||||
-rw-r--r-- | plat/arm/board/fvp/fvp_trusted_boot.c | 30 | ||||
-rw-r--r-- | plat/arm/board/fvp/include/plat.ld.S | 5 | ||||
-rw-r--r-- | plat/arm/board/fvp/include/platform_def.h | 29 | ||||
-rw-r--r-- | plat/arm/board/fvp/jmptbl.i | 3 | ||||
-rw-r--r-- | plat/arm/board/fvp/platform.mk | 56 |
14 files changed, 146 insertions, 87 deletions
diff --git a/plat/arm/board/fvp/fvp_bl1_setup.c b/plat/arm/board/fvp/fvp_bl1_setup.c index b90ddcd33..8f6170daa 100644 --- a/plat/arm/board/fvp/fvp_bl1_setup.c +++ b/plat/arm/board/fvp/fvp_bl1_setup.c @@ -48,6 +48,9 @@ void bl1_platform_setup(void) { arm_bl1_platform_setup(); + /* Initialize System level generic or SP804 timer */ + fvp_timer_init(); + /* On FVP RevC, initialize SMMUv3 */ if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U) smmuv3_security_init(PLAT_FVP_SMMUV3_BASE); diff --git a/plat/arm/board/fvp/fvp_bl2_setup.c b/plat/arm/board/fvp/fvp_bl2_setup.c index d28094993..89636d18a 100644 --- a/plat/arm/board/fvp/fvp_bl2_setup.c +++ b/plat/arm/board/fvp/fvp_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -25,15 +25,6 @@ void bl2_platform_setup(void) { arm_bl2_platform_setup(); -#if FVP_USE_SP804_TIMER - /* Enable the clock override for SP804 timer 0, which means that no - * clock dividers are applied and the raw (35 MHz) clock will be used */ - mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV); - - /* Initialize delay timer driver using SP804 dual timer 0 */ - sp804_timer_init(V2M_SP804_TIMER0_BASE, - SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); -#else - generic_delay_timer_init(); -#endif /* FVP_USE_SP804_TIMER */ + /* Initialize System level generic or SP804 timer */ + fvp_timer_init(); } diff --git a/plat/arm/board/fvp/fvp_bl2u_setup.c b/plat/arm/board/fvp/fvp_bl2u_setup.c index a8db05567..fd73767c6 100644 --- a/plat/arm/board/fvp/fvp_bl2u_setup.c +++ b/plat/arm/board/fvp/fvp_bl2u_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,6 +14,9 @@ void bl2u_early_platform_setup(struct meminfo *mem_layout, void *plat_info) { arm_bl2u_early_platform_setup(mem_layout, plat_info); + /* Initialize System level generic or SP804 timer */ + fvp_timer_init(); + /* Initialize the platform config for future decision making */ fvp_config_setup(); } diff --git a/plat/arm/board/fvp/fvp_bl31_setup.c b/plat/arm/board/fvp/fvp_bl31_setup.c index 3f92d3772..8627c5ef0 100644 --- a/plat/arm/board/fvp/fvp_bl31_setup.c +++ b/plat/arm/board/fvp/fvp_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -34,6 +34,9 @@ void __init bl31_early_platform_setup2(u_register_t arg0, */ fvp_interconnect_enable(); + /* Initialize System level generic or SP804 timer */ + fvp_timer_init(); + /* On FVP RevC, initialize SMMUv3 */ if ((arm_config.flags & ARM_CONFIG_FVP_HAS_SMMUV3) != 0U) smmuv3_init(PLAT_FVP_SMMUV3_BASE); diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c index 36cd5009a..ffaa93de4 100644 --- a/plat/arm/board/fvp/fvp_common.c +++ b/plat/arm/board/fvp/fvp_common.c @@ -10,13 +10,15 @@ #include <drivers/arm/cci.h> #include <drivers/arm/ccn.h> #include <drivers/arm/gicv2.h> +#include <drivers/arm/sp804_delay_timer.h> +#include <drivers/generic_delay_timer.h> #include <lib/mmio.h> #include <lib/xlat_tables/xlat_tables_compat.h> #include <plat/arm/common/arm_config.h> #include <plat/arm/common/plat_arm.h> #include <plat/common/platform.h> #include <platform_def.h> -#include <services/secure_partition.h> +#include <services/spm_mm_partition.h> #include "fvp_private.h" @@ -94,12 +96,9 @@ const mmap_region_t plat_arm_mmap[] = { ARM_MAP_BL1_RW, #endif #endif /* TRUSTED_BOARD_BOOT */ -#if ENABLE_SPM && SPM_MM +#if SPM_MM ARM_SP_IMAGE_MMAP, #endif -#if ENABLE_SPM && !SPM_MM - PLAT_MAP_SP_PACKAGE_MEM_RW, -#endif #if ARM_BL31_IN_DRAM ARM_MAP_BL31_SEC_DRAM, #endif @@ -120,21 +119,22 @@ const mmap_region_t plat_arm_mmap[] = { #ifdef IMAGE_BL31 const mmap_region_t plat_arm_mmap[] = { ARM_MAP_SHARED_RAM, +#if USE_DEBUGFS + /* Required by devfip, can be removed if devfip is not used */ + V2M_MAP_FLASH0_RW, +#endif /* USE_DEBUGFS */ ARM_MAP_EL3_TZC_DRAM, V2M_MAP_IOFPGA, MAP_DEVICE0, MAP_DEVICE1, ARM_V2M_MAP_MEM_PROTECT, -#if ENABLE_SPM && SPM_MM +#if SPM_MM ARM_SPM_BUF_EL3_MMAP, #endif -#if ENABLE_SPM && !SPM_MM - PLAT_MAP_SP_PACKAGE_MEM_RO, -#endif {0} }; -#if ENABLE_SPM && defined(IMAGE_BL31) && SPM_MM +#if defined(IMAGE_BL31) && SPM_MM const mmap_region_t plat_arm_secure_partition_mmap[] = { V2M_MAP_IOFPGA_EL0, /* for the UART */ MAP_REGION_FLAT(DEVICE0_BASE, \ @@ -188,12 +188,12 @@ static unsigned int get_interconnect_master(void) } #endif -#if ENABLE_SPM && defined(IMAGE_BL31) && SPM_MM +#if defined(IMAGE_BL31) && SPM_MM /* * Boot information passed to a secure partition during initialisation. Linear * indices in MP information will be filled at runtime. */ -static secure_partition_mp_info_t sp_mp_info[] = { +static spm_mm_mp_info_t sp_mp_info[] = { [0] = {0x80000000, 0}, [1] = {0x80000001, 0}, [2] = {0x80000002, 0}, @@ -204,10 +204,10 @@ static secure_partition_mp_info_t sp_mp_info[] = { [7] = {0x80000103, 0}, }; -const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = { +const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { .h.type = PARAM_SP_IMAGE_BOOT_INFO, .h.version = VERSION_1, - .h.size = sizeof(secure_partition_boot_info_t), + .h.size = sizeof(spm_mm_boot_info_t), .h.attr = 0, .sp_mem_base = ARM_SP_IMAGE_BASE, .sp_mem_limit = ARM_SP_IMAGE_LIMIT, @@ -231,7 +231,7 @@ const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) return plat_arm_secure_partition_mmap; } -const struct secure_partition_boot_info *plat_get_secure_partition_boot_info( +const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( void *cookie) { return &plat_arm_secure_partition_boot_info; @@ -407,3 +407,23 @@ int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) return arm_get_mbedtls_heap(heap_addr, heap_size); } #endif + +void fvp_timer_init(void) +{ +#if FVP_USE_SP804_TIMER + /* Enable the clock override for SP804 timer 0, which means that no + * clock dividers are applied and the raw (35MHz) clock will be used. + */ + mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV); + + /* Initialize delay timer driver using SP804 dual timer 0 */ + sp804_timer_init(V2M_SP804_TIMER0_BASE, + SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); +#else + generic_delay_timer_init(); + + /* Enable System level generic timer */ + mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, + CNTCR_FCREQ(0U) | CNTCR_EN); +#endif /* FVP_USE_SP804_TIMER */ +} diff --git a/plat/arm/board/fvp/fvp_def.h b/plat/arm/board/fvp/fvp_def.h index 1b9f84b00..347ba2e1e 100644 --- a/plat/arm/board/fvp/fvp_def.h +++ b/plat/arm/board/fvp/fvp_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -10,15 +10,15 @@ #include <lib/utils_def.h> #ifndef FVP_CLUSTER_COUNT -#define FVP_CLUSTER_COUNT 2 +#error "FVP_CLUSTER_COUNT is not set in makefile" #endif #ifndef FVP_MAX_CPUS_PER_CLUSTER -#define FVP_MAX_CPUS_PER_CLUSTER 4 +#error "FVP_MAX_CPUS_PER_CLUSTER is not set in makefile" #endif #ifndef FVP_MAX_PE_PER_CPU -# define FVP_MAX_PE_PER_CPU 1 +#error "FVP_MAX_PE_PER_CPU is not set in makefile" #endif #define FVP_PRIMARY_CPU 0x0 diff --git a/plat/arm/board/fvp/fvp_pm.c b/plat/arm/board/fvp/fvp_pm.c index 42dec8dfc..0a62543fa 100644 --- a/plat/arm/board/fvp/fvp_pm.c +++ b/plat/arm/board/fvp/fvp_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -247,10 +247,19 @@ static void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) { fvp_power_domain_on_finish_common(target_state); - /* Enable the gic cpu interface */ +} + +/******************************************************************************* + * FVP handler called when a power domain has just been powered on and the cpu + * and its cluster are fully participating in coherent transaction on the + * interconnect. Data cache must be enabled for CPU at this point. + ******************************************************************************/ +static void fvp_pwr_domain_on_finish_late(const psci_power_state_t *target_state) +{ + /* Program GIC per-cpu distributor or re-distributor interface */ plat_arm_gic_pcpu_init(); - /* Program the gic per-cpu distributor or re-distributor interface */ + /* Enable GIC CPU interface */ plat_arm_gic_cpuif_enable(); } @@ -272,7 +281,7 @@ static void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state fvp_power_domain_on_finish_common(target_state); - /* Enable the gic cpu interface */ + /* Enable GIC CPU interface */ plat_arm_gic_cpuif_enable(); } @@ -397,6 +406,7 @@ plat_psci_ops_t plat_arm_psci_pm_ops = { .pwr_domain_off = fvp_pwr_domain_off, .pwr_domain_suspend = fvp_pwr_domain_suspend, .pwr_domain_on_finish = fvp_pwr_domain_on_finish, + .pwr_domain_on_finish_late = fvp_pwr_domain_on_finish_late, .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, .system_off = fvp_system_off, .system_reset = fvp_system_reset, diff --git a/plat/arm/board/fvp/fvp_private.h b/plat/arm/board/fvp/fvp_private.h index 5067d3a2f..3590370df 100644 --- a/plat/arm/board/fvp/fvp_private.h +++ b/plat/arm/board/fvp/fvp_private.h @@ -18,6 +18,7 @@ void fvp_config_setup(void); void fvp_interconnect_init(void); void fvp_interconnect_enable(void); void fvp_interconnect_disable(void); +void fvp_timer_init(void); void tsp_early_platform_setup(void); #endif /* FVP_PRIVATE_H */ diff --git a/plat/arm/board/fvp/fvp_topology.c b/plat/arm/board/fvp/fvp_topology.c index 9823fb3b3..24e79b4d4 100644 --- a/plat/arm/board/fvp/fvp_topology.c +++ b/plat/arm/board/fvp/fvp_topology.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -36,7 +36,8 @@ const unsigned char *plat_get_power_domain_tree_desc(void) fvp_power_domain_tree_desc[1] = FVP_CLUSTER_COUNT; for (i = 0; i < FVP_CLUSTER_COUNT; i++) - fvp_power_domain_tree_desc[i + 2] = FVP_MAX_CPUS_PER_CLUSTER; + fvp_power_domain_tree_desc[i + 2] = + FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU; return fvp_power_domain_tree_desc; diff --git a/plat/arm/board/fvp/fvp_trusted_boot.c b/plat/arm/board/fvp/fvp_trusted_boot.c index 0d160cb1d..dc5076435 100644 --- a/plat/arm/board/fvp/fvp_trusted_boot.c +++ b/plat/arm/board/fvp/fvp_trusted_boot.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,39 +8,41 @@ #include <stdint.h> #include <string.h> +#include <lib/mmio.h> + #include <plat/common/platform.h> #include <platform_def.h> #include <tools_share/tbbr_oid.h> /* - * Store a new non-volatile counter value. On some FVP versions, the - * non-volatile counters are RO. On these versions we expect the values in the - * certificates to always match the RO values so that this function is never - * called. + * Store a new non-volatile counter value. + * + * On some FVP versions, the non-volatile counters are read-only so this + * function will always fail. * * Return: 0 = success, Otherwise = error */ int plat_set_nv_ctr(void *cookie, unsigned int nv_ctr) { const char *oid; - uint32_t *nv_ctr_addr; + uintptr_t nv_ctr_addr; assert(cookie != NULL); oid = (const char *)cookie; if (strcmp(oid, TRUSTED_FW_NVCOUNTER_OID) == 0) { - nv_ctr_addr = (uint32_t *)TFW_NVCTR_BASE; + nv_ctr_addr = TFW_NVCTR_BASE; } else if (strcmp(oid, NON_TRUSTED_FW_NVCOUNTER_OID) == 0) { - nv_ctr_addr = (uint32_t *)NTFW_CTR_BASE; + nv_ctr_addr = NTFW_CTR_BASE; } else { return 1; } - *(unsigned int *)nv_ctr_addr = nv_ctr; - - /* Verify that the current value is the one we just wrote. */ - if (nv_ctr != (unsigned int)(*nv_ctr_addr)) - return 1; + mmio_write_32(nv_ctr_addr, nv_ctr); - return 0; + /* + * If the FVP models a locked counter then its value cannot be updated + * and the above write operation has been silently ignored. + */ + return (mmio_read_32(nv_ctr_addr) == nv_ctr) ? 0 : 1; } diff --git a/plat/arm/board/fvp/include/plat.ld.S b/plat/arm/board/fvp/include/plat.ld.S index f024f551a..7c8bf0655 100644 --- a/plat/arm/board/fvp/include/plat.ld.S +++ b/plat/arm/board/fvp/include/plat.ld.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,9 @@ #define PLAT_LD_S #include <plat/arm/common/arm_tzc_dram.ld.S> + +#if RECLAIM_INIT_CODE #include <plat/arm/common/arm_reclaim_init.ld.S> +#endif /* RECLAIM_INIT_CODE */ #endif /* PLAT_LD_S */ diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 4f2627704..c2b7b98d4 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -17,11 +17,12 @@ #include "../fvp_def.h" /* Required platform porting definitions */ -#define PLATFORM_CORE_COUNT \ - (FVP_CLUSTER_COUNT * FVP_MAX_CPUS_PER_CLUSTER * FVP_MAX_PE_PER_CPU) +#define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ + U(FVP_MAX_CPUS_PER_CLUSTER) * \ + U(FVP_MAX_PE_PER_CPU)) -#define PLAT_NUM_PWR_DOMAINS (FVP_CLUSTER_COUNT + \ - PLATFORM_CORE_COUNT) + 1 +#define PLAT_NUM_PWR_DOMAINS (U(FVP_CLUSTER_COUNT) + \ + PLATFORM_CORE_COUNT + U(1)) #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 @@ -32,7 +33,7 @@ /* * Required ARM standard platform porting definitions */ -#define PLAT_ARM_CLUSTER_COUNT FVP_CLUSTER_COUNT +#define PLAT_ARM_CLUSTER_COUNT U(FVP_CLUSTER_COUNT) #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ @@ -61,14 +62,18 @@ * plat_arm_mmap array defined for each BL stage. */ #if defined(IMAGE_BL31) -# if ENABLE_SPM +# if SPM_MM # define PLAT_ARM_MMAP_ENTRIES 9 # define MAX_XLAT_TABLES 9 # define PLAT_SP_IMAGE_MMAP_REGIONS 30 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 # else # define PLAT_ARM_MMAP_ENTRIES 8 -# define MAX_XLAT_TABLES 5 +# if USE_DEBUGFS +# define MAX_XLAT_TABLES 6 +# else +# define MAX_XLAT_TABLES 5 +# endif # endif #elif defined(IMAGE_BL32) # define PLAT_ARM_MMAP_ENTRIES 8 @@ -94,9 +99,11 @@ #if USE_ROMLIB #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) +#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x6000) #else #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) +#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0) #endif /* @@ -104,9 +111,9 @@ * little space for growth. */ #if TRUSTED_BOARD_BOOT -# define PLAT_ARM_MAX_BL2_SIZE UL(0x1D000) +# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) #else -# define PLAT_ARM_MAX_BL2_SIZE UL(0x11000) +# define PLAT_ARM_MAX_BL2_SIZE (UL(0x11000) - FVP_BL2_ROMLIB_OPTIMIZATION) #endif /* @@ -114,11 +121,7 @@ * calculated using the current BL31 PROGBITS debug size plus the sizes of * BL2 and BL1-RW */ -#if ENABLE_SPM && !SPM_MM -#define PLAT_ARM_MAX_BL31_SIZE UL(0x60000) -#else #define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000) -#endif #ifndef __aarch64__ /* diff --git a/plat/arm/board/fvp/jmptbl.i b/plat/arm/board/fvp/jmptbl.i index bfa9b561f..6ccdd283f 100644 --- a/plat/arm/board/fvp/jmptbl.i +++ b/plat/arm/board/fvp/jmptbl.i @@ -1,5 +1,5 @@ # -# Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -19,6 +19,7 @@ fdt fdt_getprop_namelen fdt fdt_setprop_inplace fdt fdt_check_header fdt fdt_node_offset_by_compatible +fdt fdt_setprop_inplace_namelen_partial mbedtls mbedtls_asn1_get_alg mbedtls mbedtls_asn1_get_alg_null mbedtls mbedtls_asn1_get_bitstring_null diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index 0eb62c44a..97a326c09 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -99,26 +99,30 @@ ifeq (${ARCH}, aarch64) # select a different set of CPU files, depending on whether we compile for # hardware assisted coherency cores or not ifeq (${HW_ASSISTED_COHERENCY}, 0) +# Cores used without DSU FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a57.S \ lib/cpus/aarch64/cortex_a72.S \ lib/cpus/aarch64/cortex_a73.S else - # AArch64-only cores +# Cores used with DSU only ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) + # AArch64-only cores FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a76.S \ lib/cpus/aarch64/cortex_a76ae.S \ lib/cpus/aarch64/cortex_a77.S \ lib/cpus/aarch64/neoverse_n1.S \ lib/cpus/aarch64/neoverse_e1.S \ lib/cpus/aarch64/neoverse_zeus.S \ - lib/cpus/aarch64/cortex_hercules.S - # AArch64/AArch32 - else - FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ - lib/cpus/aarch64/cortex_a75.S + lib/cpus/aarch64/cortex_hercules.S \ + lib/cpus/aarch64/cortex_hercules_ae.S \ + lib/cpus/aarch64/cortex_a65.S \ + lib/cpus/aarch64/cortex_a65ae.S endif + # AArch64/AArch32 cores + FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ + lib/cpus/aarch64/cortex_a75.S endif else @@ -127,6 +131,7 @@ endif BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ drivers/arm/sp805/sp805.c \ + drivers/delay_timer/delay_timer.c \ drivers/io/io_semihosting.c \ lib/semihosting/semihosting.c \ lib/semihosting/${ARCH}/semihosting_call.S \ @@ -138,6 +143,12 @@ BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ ${FVP_CPU_LIBS} \ ${FVP_INTERCONNECT_SOURCES} +ifeq (${FVP_USE_SP804_TIMER},1) +BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c +else +BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c +endif + BL2_SOURCES += drivers/arm/sp805/sp805.c \ drivers/io/io_semihosting.c \ @@ -167,8 +178,13 @@ endif BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ ${FVP_SECURITY_SOURCES} +ifeq (${FVP_USE_SP804_TIMER},1) +BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c +endif + BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ drivers/arm/smmu/smmu_v3.c \ + drivers/delay_timer/delay_timer.c \ drivers/cfi/v2m/v2m_flash.c \ lib/utils/mem_region.c \ plat/arm/board/fvp/fvp_bl31_setup.c \ @@ -181,6 +197,12 @@ BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ ${FVP_INTERCONNECT_SOURCES} \ ${FVP_SECURITY_SOURCES} +ifeq (${FVP_USE_SP804_TIMER},1) +BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c +else +BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c +endif + # Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) ifdef UNIX_MK FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts @@ -222,15 +244,12 @@ ENABLE_AMU := 1 # Enable dynamic mitigation support by default DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 +# Enable reclaiming of BL31 initialisation code for secondary cores +# stacks for FVP. However, don't enable reclaiming for clang. ifneq (${RESET_TO_BL31},1) -# Enable reclaiming of BL31 initialisation code for secondary cores stacks for -# FVP. We cannot enable PIE for this case because the overlayed init section -# creates some dynamic relocations which cannot be handled by the fixup -# logic currently. +ifeq ($(findstring clang,$(notdir $(CC))),) RECLAIM_INIT_CODE := 1 -else -# Enable PIE support when RESET_TO_BL31=1 -ENABLE_PIE := 1 +endif endif ifeq (${ENABLE_AMU},1) @@ -264,16 +283,15 @@ else # if AArch64 ifeq (${RESET_TO_BL31},1) BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 endif - ifeq (${ENABLE_SPM},1) - ifeq (${SPM_MM},0) - BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 - endif - endif ifeq (${SPD},trusty) BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 endif endif +ifeq (${USE_DEBUGFS},1) + BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1 +endif + # Add support for platform supplied linker script for BL31 build $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT)) |