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2021-02-02docs: marvell: Add information into CLOCKSPRESET option how to identify CPU ↵Pali Rohár
frequency Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5310c30051703bbf9f377762a00eb6a8188c6fa1
2021-02-02docs: marvell: Reformat DDR_TOPOLOGY option and mention EspressoBin-Ultra boardPali Rohár
Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I96c2d9d5bc6c69a1a66a29bf586a23375d63ab5a
2021-02-02docs: marvell: Move Supported Marvell platforms to PLAT build optionPali Rohár
Reformat list of boards, remove unsupported OcteonTX2 and mention supported Turris MOX board. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I22cea7f77fd078554c7f0ed4108781626209e563
2021-01-30Merge changes from topic "sunxi-split-psci" into integrationAndré Przywara
* changes: allwinner: Leave CPU power alone during BL31 setup allwinner: psci: Invert check in .validate_ns_entrypoint allwinner: psci: Drop MPIDR check from .pwr_domain_on allwinner: psci: Drop .get_node_hw_state callback
2021-01-28Merge "tools: cert_create: Create only requested certificates" into integrationSandrine Bailleux
2021-01-28Merge "fdts: Fix stdout-path in various platforms" into integrationAndré Przywara
2021-01-27Merge "cert-tool: avoid duplicates in extension stack" into integrationLauren Wehrmeister
2021-01-27fdts: Fix stdout-path in various platformsNikos Nikoleris
The value of stdout-path is a string and as a result, we can't use a label as a reference to the serial0 node. This change fixes the stdout-path property for N1SDP, Morello and TC0 by pointing to the right alias. Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Change-Id: I3d403389a424569be56327fab4140fec06f96d37
2021-01-27Merge changes from topic "scmi-msg" into integrationMadhukar Pappireddy
* changes: doc: maintainers: add scmi server drivers: move scmi-msg out of st
2021-01-27cert-tool: avoid duplicates in extension stackJimmy Brisson
This bug manifests itself as a segfault triggered by a double-free. I noticed that right before the double-free, the sk list contained 2 elements with the same address. (gdb) p sk_X509_EXTENSION_value(sk, 1) $34 = (X509_EXTENSION *) 0x431ad0 (gdb) p sk_X509_EXTENSION_value(sk, 0) $35 = (X509_EXTENSION *) 0x431ad0 (gdb) p sk_X509_EXTENSION_num(sk) $36 = 2 This caused confusion; this should never happen. I figured that this was caused by a ext_new_xxxx function freeing something before it is added to the list, so I put a breakpoint on each of them to step through. I was suprised to find that none of my breakpoints triggered for the second element of the iteration through the outer loop just before the double-free. Looking through the code, I noticed that it's possible to avoid doing a ext_new_xxxx, when either: * ext->type == NVCOUNTER and ext->arg == NULL * ext->type == HASH and ext->arg == NULL and ext->optional == false So I put a breakpoint on both. It turns out that it was the HASH version, but I added a fix for both. The fix for the Hash case is simple, as it was a mistake. The fix for the NVCOUNTER case, however, is a bit more subtle. The NVCOUNTER may be optional, and when it's optional we can skip it. The other case, when the NVCOUNTER is required (not optinal), the `check_cmd_params` function has already verified that the `ext->arg` must be non-NULL. We assert that before processing it to covert any possible segfaults into more descriptive errors. This should no longer cause double-frees by adding the same ext twice. Change-Id: Idae2a24ecd964b0a3929e6193c7f85ec769f6470 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2021-01-27tools: cert_create: Create only requested certificatesManish V Badarkhe
The certification tool creates all the certificates mentioned statically in the code rather than taking explicit certificate requests from the command line parameters. Code is optimized to avoid unnecessary attempts to create non-requested certificates. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I78feac25bc701bf8f08c6aa5a2e1590bec92d0f2
2021-01-26Merge "Fix documentation typos and misspellings" into integrationManish Pandey
2021-01-26Merge changes from topic "tp-feat-rng" into integrationSandrine Bailleux
* changes: plat/qemu: Use RNDR in stack protector Makefile: Add FEAT_RNG support define Define registers for FEAT_RNG support
2021-01-25Merge changes I635cf82e,Iee3b4e0d into integrationLauren Wehrmeister
* changes: Makefile: Fix ${FIP_NAME} to be rebuilt only when needed Makefile: Do not mark file targets as .PHONY target
2021-01-25Merge "plat/arm: css: Turn ON/OFF redistributor in sync with GIC CPU ↵Manish Pandey
interface ON/OFF" into integration
2021-01-25doc: maintainers: add scmi serverPeng Fan
Add maintainer entry for scmi server Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: I673d7395a8cea3b553832e330c8a8ce37f8c2a5c
2021-01-24allwinner: Leave CPU power alone during BL31 setupSamuel Holland
Disabling secondary CPUs during boot is unnecessary because the other CPUs are already in reset, and it saves an entirely insignificant amount of power. Let's remove this bit of code that was added mostly "because we can", and along with it remove an unconditional dependency on the CPU ops functions. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Ia77a1b722da6ba989c3992b656a6cde3f2238fd7
2021-01-24allwinner: psci: Invert check in .validate_ns_entrypointSamuel Holland
Checking the exceptional case and letting the success case fall through is not only more idiomatic, but it also allows adding more exceptional cases in the future, such as a check for overlapping secure DRAM. Change-Id: I720441a6a8853fd7f211ebe851f14d921a6db03d Signed-off-by: Samuel Holland <samuel@sholland.org>
2021-01-24allwinner: psci: Drop MPIDR check from .pwr_domain_onSamuel Holland
This duplicated the logic in psci_validate_mpidr() which was already called from psci_cpu_on(). Change-Id: I96ee92f1ce3e9cc2985b4e229ba86ebd27b79915 Signed-off-by: Samuel Holland <samuel@sholland.org>
2021-01-24allwinner: psci: Drop .get_node_hw_state callbackSamuel Holland
This optional PSCI function was only implemented when SCPI was available. However, the underlying SCPI function is not able to fulfill the necessary contract. First, the SCPI protocol has no way to represent HW_STANDBY at the CPU power level. Second, the SCPI implementation maintains its own logical view of power states, and its implementation of SCPI_CMD_GET_CSS_POWER_STATE does not actually query the hardware. Thus it cannot provide "the physical view of power state", as required for this function by the PSCI specification. Since the function is optional, drop it. Change-Id: I5f3a0810ac19ddeb3c0c5d35aeb09f09a0b80c1d Signed-off-by: Samuel Holland <samuel@sholland.org>
2021-01-24Merge "docs: marvell: armada: Update MARVELL_PLATFORM list and build ↵Madhukar Pappireddy
instructions" into integration
2021-01-22Merge "stm32mp1: correct plat_crash_console_flush()" into integrationMadhukar Pappireddy
2021-01-22Merge "DebugFS: Check channel index before calling clone function" into ↵Olivier Deprez
integration
2021-01-22stm32mp1: correct plat_crash_console_flush()Yann Gautier
The base address of UART peripheral should be given in R0, not in R1. Otherwise the console_stm32_core_flush issues an assert message. This issue was highlighted with recent changes in console flush functions. Change-Id: Iead01986fdbbf30ad2fd9fa515a1d2b611b4e591 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2021-01-21Merge changes I2add6b4b,I9b296372,I7af2f1d1 into integrationMadhukar Pappireddy
* changes: libc/snprintf: use macro to reduce duplicated code libc/snprintf: add support to print "%" character libc/printf: add support to print "%" character
2021-01-21DebugFS: Check channel index before calling clone functionZelalem
To avoid a potential out-of-bounds access, check whether a device exists on a channel before calling the corresponding clone function. Signed-off-by: Zelalem <zelalem.aweke@arm.com> Change-Id: Ia0dd66b331d3fa8a33109a02369e1bc9ae0fdd5b
2021-01-21Fix documentation typos and misspellingsDavid Horstmann
Fix some typos and misspellings in TF-A documentation. Signed-off-by: David Horstmann <david.horstmann@arm.com> Change-Id: Id72553ce7b2f0bed9821604fbc8df4d4949909fa
2021-01-20Merge changes I44ef50da,I9802e9a3 into integrationManish Pandey
* changes: plat/arm/css/sgi: Fix assert expression issue plat/arm/css/sgi: Fix bl32 receive event - 0xC4000061 issue
2021-01-20Merge "plat: xilinx: versal: Remove code duplication" into integrationMadhukar Pappireddy
2021-01-20plat/arm/css/sgi: Fix assert expression issueMing Huang
Violation of MISRA-C Rule 14.4 Signed-off-by: Ming Huang <huangming@linux.alibaba.com> Change-Id: I44ef50dadb54fb056a91f3de962b6e63ba6d7ac4
2021-01-20plat/arm/css/sgi: Fix bl32 receive event - 0xC4000061 issueMing Huang
The issue is that, when interrupt is triggered and RAS handler is entered, after interrupt handler finishes, TF-A will re-enter bl32 and then crash. sdei_dispatch_event() may return failing result in some cases, for example kernel may not have registered a handler or RAS event may happen early during boot. We restore the NS context when sdei_dispatch_event() returns failing result. error log : Received delegated event X0 : 0xC4000061 X1 : 0x0 X2 : 0x0 X3 : 0x0 Received event - 0xC4000061 on cpu 0 UnRecognized Event - 0xC4000061 Failed delegated event 0xC4000061, Status Invalid Parameter Unhandled Exception in EL3. x30 = 0x000000000401f700 x0 = 0xfffffffffffffffe x1 = 0xfffffffffffffffe x2 = 0x00000000600003c0 Signed-off-by: Ming Huang <huangming@linux.alibaba.com> Change-Id: I9802e9a32eee0ac3b5a8bcc0362d0b0e3b71dc9f
2021-01-20Merge changes Ic9bacaf3,I99a18dbb,I34803060,I3ed55aa4,Ic8eed072, ... into ↵Manish Pandey
integration * changes: doc: renesas: Update RZ/G2 code owner list plat: renesas: rzg: DT memory node enhancements renesas: rzg: emmc: Enable RZ/G2M support plat: renesas: rzg: Add HopeRun HiHope RZ/G2M board support drivers: renesas: rzg: Add HiHope RZ/G2M board support tools: renesas: Add tool support for RZ/G2 platforms
2021-01-20Merge changes I19e4e7f5,I226b6e33 into integrationMadhukar Pappireddy
* changes: marvell: uart: a3720: Fix macro name for 6th bit of Status Register marvell: uart: a3720: Implement console_a3700_core_getc
2021-01-20Merge changes from topic "qemu-sbsa-topology-psci" into integrationMadhukar Pappireddy
* changes: qemu/qemu_sbsa: add support for sbsa-ref Embedded Controller qemu/qemu_sbsa: topology is different from qemu so add handling qemu/common : change DEVICE2 definition for MMU qemu/aarch64/plat_helpers.S : calculate the position shift
2021-01-20plat/arm: css: Turn ON/OFF redistributor in sync with GIC CPU interface ON/OFFJagadeesh Ujja
Turn ON/OFF GIC redistributor in sync with GIC CPU interface ON/OFF. Issue : The Linux prompt hangs when all the cores in a cluster are turned OFF and we try to turn ON a core in that cluster. Previously when TF-A turns ON a core, TF-A first turns ON the redistributor followed by the core. This did not match the flow when turning OFF a core, as TF-A did not turn OFF redistributor when the corresponding core[s] are disabled. This hang is resolved by disabling redistributor as cores are disabled, keeping them in sync. Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com> Change-Id: Ifd04fdcfd47b45e00f874f15b098471883d023f0
2021-01-20plat: xilinx: versal: Remove code duplicationRajan Vaja
Some switch cases uses same operation. So, club switch cases which uses same operation and remove duplicate code. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Change-Id: I260b474c0ff3f2ca102c32d4af2e4abba2b8f57c
2021-01-20libc/snprintf: use macro to reduce duplicated codeHeyi Guo
Add macro CHECK_AND_PUT_CHAR to check buffer capacity, save one character to buffer, and then increase character counter by one in one single statement, so that 4 similar code pieces can be cleaned. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I2add6b4bd6c24ea3c0d2499a44924e3e8db0f4d1
2021-01-20libc/snprintf: add support to print "%" characterHeyi Guo
Enable snprintf()/vsnprintf() in TF-A to print "%" character as C standard, which may be used in platform porting to print percentage information. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I9b296372a1002046eabac1df5e8eb99a27efd4a8
2021-01-20libc/printf: add support to print "%" characterHeyi Guo
Enable printf() in TF-A to print "%" character as C standard, which may be used in platform porting to print percentage information. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I7af2f1d153548e426f423fce15dc48b0da56c622
2021-01-20drivers: move scmi-msg out of stPeng Fan
Make the scmi-msg driver reused by others. Signed-off-by: Peng Fan <peng.fan@nxp.com> Change-Id: I5bc35fd4dab70f45c09b8aab65af4209cf23b124
2021-01-19qemu/qemu_sbsa: add support for sbsa-ref Embedded ControllerGraeme Gregory
This allows PSCI in TF-A to signal platform power states to QEMU via a controller in secure space. This required a sbsa-ref specific version of PSCI functions for the platform. Also adjusted the MMU range to also include the new EC. Add a new MMU region for the embedded controller and increase the size of xlat tables by one for the new region. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: Iece8a88947f11e82ab8988e460a8a66ad175a5ee
2021-01-19qemu/qemu_sbsa: topology is different from qemu so add handlingGraeme Gregory
sbsa-ref in QEMU creates clusers of 8 cores, it may create up to 512 cores in upto 64 clusters. Implement a qemu_sbsa specific topology file and increase the BL31_SIZE to accommodate the bigger table sizes. Change platform_def.h for new topology. Correct PLATFORM_CPU_PER_CLUSTER_SHIFT so plat_helpers.S calculates correct result. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: Idc5d70394c0956b759ad2c86f9fda8f293f2cfa7
2021-01-19qemu/common : change DEVICE2 definition for MMUGraeme Gregory
DEVICE2 is not currently used on qemu platform but is needed for a future patch for qemu_sbsa platform. Change its definition to RW and add it to all levels of arm-tf similar to DEVICE1 definition. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: I03495471bfd423b61ad44ec4953fb25f76aa54bf
2021-01-19qemu/aarch64/plat_helpers.S : calculate the position shiftGraeme Gregory
Rather than re-create this file in multiple qemu variants instead caclulate the shift needed to convert MPIDR to position. Add a new PLATFORM_CPU_PER_CLUSTER_SHIFT define in platform_def.h for both qemu and qemu_sbsa to enable this calculation. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: I0e3a86354aa716d95150a3a34b15287cd70c8fd2
2021-01-19Merge "fdts: stm32mp1: add support for Linux Automation MC-1 board" into ↵Madhukar Pappireddy
integration
2021-01-19plat/qemu: Use RNDR in stack protectorTomas Pilar
When getting a stack protector canary value, check if cpu supports FEAT_RNG and use that. Fallback to old method of using a (hardcoded value ^ timer). Signed-off-by: Tomas Pilar <tomas@nuviainc.com> Change-Id: I8181acf8e31661d4cc82bc3a4078f8751909e725
2021-01-19fdts: stm32mp1: add support for Linux Automation MC-1 boardAhmad Fatoum
The Linux Automation MC-1 is a SBC built around the Octavo Systems OSD32MP15x SiP. The SiP features up to 1 GB DDR3 RAM, EEPROM and PMIC. The board has eMMC and a SD slot for storage. The SDRAM calibration values are taken as is from the DKx boards, which seem to be suitable for operation at German room temperature. This is deemed ok for now, but for use in the field, the SiP will likely need to have its timings determined in a climate chamber. Change-Id: I5f43a61930151ae9d1df2ea7d0f6f9697c813ce0 Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
2021-01-18marvell: uart: a3720: Fix macro name for 6th bit of Status RegisterPali Rohár
This patch does not change code, it only updates comments and macro name for 6th bit of Status Register. So TF-A binary stay same. 6th bit of the Status Register is named TX EMPTY and is set to 1 when both Transmitter Holding Register (THR) or Transmitter Shift Register (TSR) are empty. It is when all characters were already transmitted. There is also TX FIFO EMPTY bit in the Status Register which is set to 1 only when THR is empty. In both console_a3700_core_init() and console_a3700_core_flush() functions we should wait until both THR and TSR are empty therefore we should check 6th bit of the Status Register. So current code is correct, just had misleading macro names and comments. This change fixes this "documentation" issue, fixes macro name for 6th bit of the Status Register and also updates comments. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I19e4e7f53a90bcfb318e6dd1b1249b6cbf81c4d3
2021-01-18marvell: uart: a3720: Implement console_a3700_core_getcPali Rohár
Implementation is simple, just check if there is a pending character in RX FIFO via RXRDY bit of Status Register and if yes, read it from UART_RX_REG register. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I226b6e336f44f5d0ca8dcb68e49a68e8f2f49708
2021-01-15Merge changes I3c0a402f,I9ce5b9df,I08719015,If541278f,I99f1a697 into integrationMadhukar Pappireddy
* changes: doc: renesas: Update code owner for Renesas platforms doc: renesas: Document platforms based on RZ/G2 SoC's renesas: rzg: Add PFC support for RZ/G2M renesas: rzg: Add QoS support for RZ/G2M renesas: rzg: Add support for DRAM initialization
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