aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2021-04-20fix: plat: marvell: fix MSS loader for A8K familyKonstantin Porotchkin
Wrong brakets caused MSS FW load timeout error: ERROR: MSS DMA failed (timeout) ERROR: MSS FW chunk 0 load failed ERROR: SCP Image load failed This patch fixes the operator precedence in MSS FW load. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: I78c215606bde112f40429926c51f5fa1e4334c13
2021-04-19Merge "services: spm_mm: Use sp_boot_info to set SP context" into integrationManish Pandey
2021-04-19services: spm_mm: Use sp_boot_info to set SP contextMayur Gudmeti
The current SPM_MM implementations expects the SP image addresses as static macros. This means platforms wanting to use dynamically allocated memory addresses are left out. This patch gets sp_boot_info at the beginning of spm_sp_setup function and uses member variables of sp_boot_info to setup the context. So member variables of struct sp_boot_info and consequently the context can be initialized by static macros or dynamiclly allocated memory address.. Change-Id: I1cb75190ab8026b845ae20a9c6cc416945b5d7b9 Signed-off-by: Mayur Gudmeti <mgudmeti@nvidia.com>
2021-04-16Merge "docs: Update Mbed TLS supported version" into integrationSandrine Bailleux
2021-04-15Merge changes from topic "scmi_v2_0" into integrationMadhukar Pappireddy
* changes: drivers/arm/css/scmi: Update power domain protocol version to 2.0 tc0: update GICR base address
2021-04-14drivers/arm/css/scmi: Update power domain protocol version to 2.0Nicola Mazzucato
The SCMI power domain protocol in firmware has been updated to v2.0, thus update the corresponding version in TF-A too. Signed-off-by: Nicola Mazzucato <nicola.mazzucato@arm.com> Change-Id: If3920ff71136dce94b2780e29a47f24aa09876c0
2021-04-14tc0: update GICR base addressUsama Arif
The number of ITS have changed from 4 to 1, resulting in GICR base address change. Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: I28101f0d1faf9f3c58591b642033c3fd49a275e7
2021-04-14docs: Update Mbed TLS supported versionManish V Badarkhe
Updated the documentation with latest Mbed TLS supported version i.e. Mbed TLS v2.26.0 Fixes available in this version of Mbed TLS mainly affect key generation/writing and certificates writing, which are features used in the cert_create tool. Release notes of Mbed TLSv2.26.0 are available here: https://github.com/ARMmbed/mbedtls/releases/tag/v2.26.0 Change-Id: Ie15ee45d878b7681e15ec4bf64d54b416a31aa2f Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-04-13Merge changes from topic "dcc_console" into integrationMadhukar Pappireddy
* changes: plat:xilinx:versal: Add JTAG DCC support plat:xilinx:zynqmp: Add JTAG DCC support drivers: dcc: Support JTAG DCC console
2021-04-13Merge "plat/arm: don't provide NT_FW_CONFIG when booting hafnium" into ↵Olivier Deprez
integration
2021-04-13Merge "fiptool: Do not print duplicate verbose lines about building fiptool" ↵Madhukar Pappireddy
into integration
2021-04-12Merge "driver: brcm: add USB driver" into integrationMadhukar Pappireddy
2021-04-12Merge "driver: brcm: add mdio driver" into integrationMadhukar Pappireddy
2021-04-12Merge "arch: Enable `FEAT_SB` for supported non-Armv8.5-A platforms" into ↵Olivier Deprez
integration
2021-04-09plat/arm: don't provide NT_FW_CONFIG when booting hafniumManish Pandey
NT_FW_CONFIG file is meant to be passed from BL31 to be consumed by BL33, fvp platforms use this to pass measured boot configuration and the x0 register is used to pass the base address of it. In case of hafnium used as hypervisor in normal world, hypervisor manifest is expected to be passed from BL31 and its base address is passed in x0 register. As only one of NT_FW_CONFIG or hypervisor manifest base address can be passed in x0 register and also measured boot is not required for SPM so disable passing NT_FW_CONFIG. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ifad9d3658f55ba7d70f468a88997d5272339e53e
2021-04-09Merge changes from topic "mmc_device_info" into integrationMadhukar Pappireddy
* changes: plat/st: do not keep mmc_device_info in stack plat/intel: do not keep mmc_device_info in stack plat/hisilicon: do not keep mmc_device_info in stack
2021-04-08Merge changes from topic "mmc_device_info" into integrationMadhukar Pappireddy
* changes: mmc: remove useless extra semicolons Revert "mmc:prevent accessing to the released space in case of wrong usage"
2021-04-08fiptool: Do not print duplicate verbose lines about building fiptoolPali Rohár
Makefile for fiptool already prints verbose line when is (re)building fiptool, so there is no need to print it also from top level Makefile. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I6936a508702f1bf796d17578bb1f043f06365319
2021-04-08Merge "fiptool: Do not call 'make clean' in 'all' target" into integrationManish Pandey
2021-04-08plat/st: do not keep mmc_device_info in stackYann Gautier
Create a dedicated static struct mmc_device_info mmc_info mmc_info instead of having this in stack. A boot issue has been seen on some platform when applying patch [1]. [1] 13f3c5166f1 ("mmc:prevent accessing to the released space in case of wrong usage") Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: I73a079715253699d903721c865d6470d58f6bd30
2021-04-08mmc: remove useless extra semicolonsYann Gautier
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: If1d6b2040e482577292890e3554449096648c2ae
2021-04-08plat/intel: do not keep mmc_device_info in stackYann Gautier
Create a dedicated static struct mmc_device_info mmc_info mmc_info instead of having this in stack. A boot issue has been seen on some platform when applying patch [1]. [1] 13f3c5166f1 ("mmc:prevent accessing to the released space in case of wrong usage") Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: Id52c0be61a30f453a551385883eaf3cbe32b04b9
2021-04-08Revert "mmc:prevent accessing to the released space in case of wrong usage"Yann Gautier
This reverts commit 13f3c5166f126b021e5f6e09e4a7c97f12495a35. The STM32MP1 platform can no more boot qwith this change. The driver will not be aware when the static struct in framework is updated. Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: Icc544e243136ee3b0067f316b71dff7dfd6526d6
2021-04-08plat/hisilicon: do not keep mmc_device_info in stackYann Gautier
Create a dedicated static struct mmc_device_info mmc_info mmc_info instead of having this in stack. A boot issue has been seen on some platform when applying patch [1]. [1] 13f3c5166f1 ("mmc:prevent accessing to the released space in case of wrong usage") Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: If5db8857cccec2e677b16a38eb3eeb41628a264c
2021-04-07Merge "lib/cpu: Workaround for Cortex A77 erratum 1946167" into integrationMadhukar Pappireddy
2021-04-07Merge "Fix: Remove save/restore of EL2 timer registers" into integrationOlivier Deprez
2021-04-07fiptool: Do not call 'make clean' in 'all' targetPali Rohár
Calling 'make clean' in 'all' target is causing recompilation of binary at every 'make' call, which is wrong. Also building a new target via 'make TARGET' can cause infinite loop as it is not defined as explicit make dependency. Dependent targets must be specified after colon when defining target, which also prevents infinite loops as make is able to detect these circular dependencies. Moreover calling 'make clean' is supposed to be done by user when configuration is changing. So remove calling 'make clean' in 'all' target and define dependency for '${PROJECT}' at correct place. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I70e7fd2b04b02f6a0650c82df91d58c9a4cb24d9
2021-04-07Merge changes Id2a538c3,Ifa0339e7,I8b09fab8 into integrationMadhukar Pappireddy
* changes: drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initialization drivers: marvell: comphy-a3700: Set mask parameter for every reg_set call drivers: marvell: comphy-a3700: Fix configuring polarity invert bits
2021-04-07Merge changes from topic "my-topic-name" into integrationMadhukar Pappireddy
* changes: plat: imx8mm: Add image load logic for TBBR FIP booting plat: imx8mm: Add initial defintions to facilitate FIP layout plat: imx8mm: Add image io-storage logic for TBBR FIP booting plat: imx8mm: Add imx8mm_private.h to the build
2021-04-07Fix: Remove save/restore of EL2 timer registersMax Shvetsov
Since there is a secure and non-secure version of the timer registers there is no need to preserve their context in EL3. With that, following registers were removed from EL3 save/restore routine: cnthps_ctl_el2 cnthps_tval_el2 cnthps_cval_el2 cnthvs_ctl_el2 cnthvs_tval_el2 cnthvs_cval_el2 cnthp_ctl_el2 cnthp_cval_el2 cnthp_tval_el2 cnthv_ctl_el2 cnthv_cval_el2 cnthv_tval_el2 Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: I6e2fc09c74a7375c4fccc11f12af4e39e6dc616b
2021-04-07Merge changes I4061428b,Icaee5da1 into integrationManish Pandey
* changes: plat/arm/arm_image_load: refine plat_add_sp_images_load_info plat/arm/arm_image_load: fix bug of overriding the last node
2021-04-06drivers: marvell: comphy-a3700: Set TXDCLK_2X_SEL bit during PCIe initializationPali Rohár
Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe Root Complex mode. Both U-Boot and Linux kernel support only Root Complex mode. Set this bit. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Id2a538c379b911b62597f9463b4842b7b5c24df7
2021-04-06drivers: marvell: comphy-a3700: Set mask parameter for every reg_set callPali Rohár
The third argument of the reg_set() function has name 'mask', which indicates that it is a mask applied to the register value which is going to be updated. But the implementation of this function uses this argument to clear prior value of the register, i.e. instead of new_val = (old_val & ~mask) | (data & mask); it does new_val = (new_val & ~mask) | data; (The more proper name for this function should be reg_clrsetbits(), since internally it calls mmio_clrsetbits_32().) To make code more readable set 'mask' argument to real mask, i.e. bits of register values which are going to be updated. This patch does not make any functional change, only cosmetic, due to how 'mask' is interpreted. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Ifa0339e79c07d1994c7971b65d966b92cb735f65
2021-04-06drivers: marvell: comphy-a3700: Fix configuring polarity invert bitsPali Rohár
TXD_INVERT_BIT or RXD_INVERT_BIT needs to be set only in case when appropriate polarity is inverted. Otherwise these bits should be cleared. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I8b09fab883a7b995fd72a7d8ae6233f0fa07011b
2021-04-06plat/arm/arm_image_load: refine plat_add_sp_images_load_infoHeyi Guo
Refine the function plat_add_sp_images_load_info() by saving the previous node and only setting its next link when the current node is valid. This can reduce the check for the next node and simply the total logic. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I4061428bf49ef0c3816ac22aaeb2e50315531f88
2021-04-06plat/arm/arm_image_load: fix bug of overriding the last nodeHeyi Guo
The traverse flow in function plat_add_sp_images_load_info() will find the last node in the main load info list, with its next_load_info==NULL. However this node is still useful and should not be overridden with SP node info. The bug will cause below error on RDN2 for spmd enabled: ERROR: Invalid NT_FW_CONFIG DTB passed Fix the bug by only setting the next_load_info of the last node in the original main node list. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: Icaee5da1f2d53b29fdd6085a8cc507446186fd57
2021-04-06lib/cpu: Workaround for Cortex A77 erratum 1946167laurenw-arm
Cortex A77 erratum 1946167 is a Cat B erratum that applies to revisions <= r1p1. This erratum is avoided by inserting a DMB ST before acquire atomic instructions without release semantics through a series of writes to implementation defined system registers. SDEN can be found here: https://documentation-service.arm.com/static/600057a29b9c2d1bb22cd1be?token= Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I53e3b4fb7e7575ec83d75c2f132eda5ae0b4f01f
2021-04-06Merge "Add Cortex_A78C CPU lib" into integrationMadhukar Pappireddy
2021-03-31plat:xilinx:versal: Add JTAG DCC supportVenkatesh Yadav Abbarapu
As per the new multi-console framework, updating the JTAG DCC support. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Change-Id: I77994ce387caf0d695986df3d01d414a920978d0
2021-03-31plat:xilinx:zynqmp: Add JTAG DCC supportVenkatesh Yadav Abbarapu
As per the new multi-console framework, updating the JTAG DCC support. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Change-Id: I62cfbb57ae7e454fbc91d1c54aafa6e99f9a35c8
2021-03-31drivers: dcc: Support JTAG DCC consoleVenkatesh Yadav Abbarapu
The legacy console is gone. Re-add DCC console support based on the multi-console framework. Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Change-Id: Ia8388721093bc1be3af40974530d7c9a9ae5f43e
2021-03-31Add Cortex_A78C CPU libBipin Ravi
Add basic support for Cortex_A78C CPU. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Id9e41cbe0580a68c6412d194a5ee67940e8dae56
2021-03-30Merge changes from topic "allwinner_h616" into integrationAndré Przywara
* changes: allwinner: H616: Add reserved-memory node to DT allwinner: Add Allwinner H616 SoC support allwinner: Add H616 SoC ID allwinner: Express memmap more dynamically allwinner: Move sunxi_cpu_power_off_self() into platforms allwinner: Move SEPARATE_NOBITS_REGION to platforms doc: allwinner: Reorder sections, document memory mapping
2021-03-29Merge "Add Makalu ELP CPU lib" into integrationbipin.ravi
2021-03-29Merge changes from topic "rd_updates" into integrationMadhukar Pappireddy
* changes: plat/sgi: allow usage of secure partions on rdn2 platform board/rdv1mc: initialize tzc400 controllers plat/sgi: allow access to TZC controller on all chips plat/sgi: define memory regions for multi-chip platforms plat/sgi: allow access to nor2 flash and system registers from s-el0 plat/sgi: define default list of memory regions for dmc620 tzc plat/sgi: improve macros defining cper buffer memory region plat/sgi: refactor DMC-620 error handling SMC function id plat/sgi: refactor SDEI specific macros
2021-03-29plat/sgi: allow usage of secure partions on rdn2 platformOmkar Anand Kulkarni
Add the secure partition mmap table and the secure partition boot information to support secure partitions on RD-N2 platform. In addition to this, add the required memory region mapping for accessing the SoC peripherals from the secure partition. Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com> Change-Id: I2c75760d6c8c3da3ff4885599be420e924aeaf3c
2021-03-29Merge changes from topic "tzc400_stm32mp" into integrationSandrine Bailleux
* changes: stm32mp1: add TZC400 interrupt management stm32mp1: use TZC400 macro to describe filters tzc400: add support for interrupts
2021-03-29board/rdv1mc: initialize tzc400 controllersAditya Angadi
A TZC400 controller is placed inline on DRAM channels and regulates the secure and non-secure accesses to both secure and non-secure regions of the DRAM memory. Configure each of the TZC controllers across the Chips. For use by secure software, configure the first chip's trustzone controller to protect the upper 16MB of the memory of the first DRAM block for secure accesses only. The other regions are configured for non-secure read write access. For all the remote chips, all the DRAM regions are allowed for non-secure read and write access. Signed-off-by: Aditya Angadi <aditya.angadi@arm.com> Change-Id: I809f27eccadfc23ea0ef64e2fd87f95eb8f195c1
2021-03-29plat/sgi: allow access to TZC controller on all chipsAditya Angadi
On a multi-chip platform, the boot CPU on the first chip programs the TZC controllers on all the remote chips. Define a memory region map for the TZC controllers for all the remote chips and include it in the BL2 memory map table. In addition to this, for SPM_MM enabled multi-chip platforms, increase the number of mmap entries and xlat table counts for EL3 execution context as well because the shared RAM regions and GIC address space of remote chips are accessed. Signed-off-by: Aditya Angadi <aditya.angadi@arm.com> Change-Id: I6f0b5fd22f9f28046451e382eef7f1f9258d88f7
2021-03-29plat/sgi: define memory regions for multi-chip platformsAditya Angadi
For multi-chip platforms, add a macro to define the memory regions on chip numbers >1 and its associated access permissions. These memory regions are marked with non-secure access. Signed-off-by: Aditya Angadi <aditya.angadi@arm.com> Change-Id: If3d6180fd8ea61f45147c39d3140d694abf06617
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-08 10:15:13 +0000