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2021-04-07Merge "lib/cpu: Workaround for Cortex A77 erratum 1946167" into integrationMadhukar Pappireddy
2021-04-07Merge "Fix: Remove save/restore of EL2 timer registers" into integrationOlivier Deprez
2021-04-07Fix: Remove save/restore of EL2 timer registersMax Shvetsov
Since there is a secure and non-secure version of the timer registers there is no need to preserve their context in EL3. With that, following registers were removed from EL3 save/restore routine: cnthps_ctl_el2 cnthps_tval_el2 cnthps_cval_el2 cnthvs_ctl_el2 cnthvs_tval_el2 cnthvs_cval_el2 cnthp_ctl_el2 cnthp_cval_el2 cnthp_tval_el2 cnthv_ctl_el2 cnthv_cval_el2 cnthv_tval_el2 Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Change-Id: I6e2fc09c74a7375c4fccc11f12af4e39e6dc616b
2021-04-06lib/cpu: Workaround for Cortex A77 erratum 1946167laurenw-arm
Cortex A77 erratum 1946167 is a Cat B erratum that applies to revisions <= r1p1. This erratum is avoided by inserting a DMB ST before acquire atomic instructions without release semantics through a series of writes to implementation defined system registers. SDEN can be found here: https://documentation-service.arm.com/static/600057a29b9c2d1bb22cd1be?token= Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: I53e3b4fb7e7575ec83d75c2f132eda5ae0b4f01f
2021-03-31Add Cortex_A78C CPU libBipin Ravi
Add basic support for Cortex_A78C CPU. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: Id9e41cbe0580a68c6412d194a5ee67940e8dae56
2021-03-24Add Makalu ELP CPU libjohpow01
Add basic support for Makalu ELP processor core. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I7b1ddbb8dd43326ecb8ff188f6f8fcf239826a93
2021-03-10cpus: add Matterhorn ELP ARM cpu libraryUsama Arif
Change-Id: Ie1acde619a5b21e09717c0e80befb6d53fd16607 Signed-off-by: Usama Arif <usama.arif@arm.com>
2021-03-02Merge "Add Makalu CPU lib" into integrationbipin.ravi
2021-03-02Merge "lib/extensions/ras: fix bug of binary search" into integrationManish Pandey
2021-03-01Add Makalu CPU libjohpow01
Add basic support for Makalu CPU. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I4e85d425eedea499adf585eb8ab548931185043d
2021-02-25Enable v8.6 AMU enhancements (FEAT_AMUv1p1)johpow01
ARMv8.6 adds virtual offset registers to support virtualization of the event counters in EL1 and EL0. This patch enables support for this feature in EL3 firmware. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I7ee1f3d9f554930bf5ef6f3d492e932e6d95b217
2021-02-24libc: memset: Fix MISRA issuesAndre Przywara
MISRA complained about "0"s not being followed by an "U" (please note my protest about this!) and about values not being explicitly compared to 0 (fair enough). Also use explicit pointer types. Fix those issues to make the CI happy. Change-Id: I4d11e49c14f16223a71c78b0fc3e68ba9a1382d3 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-02-23lib: cpus: aarch32: sanity check pointers before useYann Gautier
This is the AARCH32 update of patch [1]. [1] 601e3ed209eb ("lib: cpus: sanity check pointers before use") Signed-off-by: Yann Gautier <yann.gautier@foss.st.com> Change-Id: I43dbe00a5802a7e1c6f877e22d1c66ec8275c6fa
2021-02-11Merge changes from topic "mp/strto_libc" into integrationMadhukar Pappireddy
* changes: libc: Import strtoull from FreeBSD project libc: Import strtoll from FreeBSD project libc: Import strtoul from FreeBSD project libc: Import strtol from FreeBSD project
2021-02-05rainier: remove cpu workaround for errata 1542419Manoj Kumar
This patch removes the Neoverse N1 CPU errata workaround for bug 1542419 as the bug is not present in Rainier R0P0 core. Change-Id: Icaca299b13ef830b2ee5129576aae655a6288e69 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
2021-02-03libc: Import strtoull from FreeBSD projectMadhukar Pappireddy
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b The coding guidelines[1] in TF-A forbid the use of ato*() functions in favour of strto*(). However, the TF-A libc does not provide an implementation of strto*(), making this rule impossible to satisfy. Also made small changes to fit into TF-A project. Added the source files to the libc makefile [1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution Change-Id: I2e94a0b227ec39f6f4530dc50bb477999d27730f Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-02-03libc: Import strtoll from FreeBSD projectMadhukar Pappireddy
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b The coding guidelines[1] in TF-A forbid the use of ato*() functions in favour of strto*(). However, the TF-A libc does not provide an implementation of strto*(), making this rule impossible to satisfy. Also made small changes to fit into TF-A project. Added the source files to the libc makefile [1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution Change-Id: I9cb581574d46de73c3d6917ebf78935fc5ac075a Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-02-03libc: Import strtoul from FreeBSD projectMadhukar Pappireddy
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b The coding guidelines[1] in TF-A forbid the use of ato*() functions in favour of strto*(). However, the TF-A libc does not provide an implementation of strto*(), making this rule impossible to satisfy. Also made small changes to fit into TF-A project. Added the source files to the libc makefile [1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution Change-Id: I8c3b92751d1ce226c966f7c81fedd83f0846865e Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-02-03libc: Import strtol from FreeBSD projectMadhukar Pappireddy
From commit: 21571b1d140ae7bb44e94c0afba2ec61456b275b The coding guidelines[1] in TF-A forbid the use of ato*() functions in favour of strto*(). However, the TF-A libc does not provide an implementation of strto*(), making this rule impossible to satisfy. Also made small changes to fit into TF-A project. Added the source files to the libc makefile [1] https://trustedfirmware-a.readthedocs.io/en/latest/process/coding-guidelines.html#libc-functions-that-are-banned-or-to-be-used-with-caution Change-Id: Ica95bf5da722913834fe90bf3fe743aa34e01e80 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-01-29Fix exception handlers in BL31: Use DSB to synchronize pending EAMadhukar Pappireddy
For SoCs which do not implement RAS, use DSB as a barrier to synchronize pending external aborts at the entry and exit of exception handlers. This is needed to isolate the SErrors to appropriate context. However, this introduces an unintended side effect as discussed in the https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/3440 A summary of the side effect and a quick workaround is provided as part of this patch and summarized here: The explicit DSB at the entry of various exception vectors in BL31 for handling exceptions from lower ELs can inadvertently trigger an SError exception in EL3 due to pending asyncrhonouus aborts in lower ELs. This will end up being handled by serror_sp_elx in EL3 which will ultimately panic and die. The way to workaround is to update a flag to indicate if the exception truly came from EL3. This flag is allocated in the cpu_context structure. This is not a bullet proof solution to the problem at hand because we assume the instructions following "isb" that help to update the flag (lines 100-102 & 139-141) execute without causing further exceptions. Change-Id: I4d345b07d746a727459435ddd6abb37fda24a9bf Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2021-01-22Merge "DebugFS: Check channel index before calling clone function" into ↵Olivier Deprez
integration
2021-01-21DebugFS: Check channel index before calling clone functionZelalem
To avoid a potential out-of-bounds access, check whether a device exists on a channel before calling the corresponding clone function. Signed-off-by: Zelalem <zelalem.aweke@arm.com> Change-Id: Ia0dd66b331d3fa8a33109a02369e1bc9ae0fdd5b
2021-01-20libc/snprintf: use macro to reduce duplicated codeHeyi Guo
Add macro CHECK_AND_PUT_CHAR to check buffer capacity, save one character to buffer, and then increase character counter by one in one single statement, so that 4 similar code pieces can be cleaned. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I2add6b4bd6c24ea3c0d2499a44924e3e8db0f4d1
2021-01-20libc/snprintf: add support to print "%" characterHeyi Guo
Enable snprintf()/vsnprintf() in TF-A to print "%" character as C standard, which may be used in platform porting to print percentage information. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I9b296372a1002046eabac1df5e8eb99a27efd4a8
2021-01-20libc/printf: add support to print "%" characterHeyi Guo
Enable printf() in TF-A to print "%" character as C standard, which may be used in platform porting to print percentage information. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: I7af2f1d153548e426f423fce15dc48b0da56c622
2021-01-14lib/extensions/ras: fix bug of binary searchHeyi Guo
In ras_interrupt_handler(), binary search end was set to the size of the ras_interrupt_mappings array, which would cause out of bound access when the input intr_raw is larger than all the elements in ras_interrupt_mappings. Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: Id2cff73177134b09d4d8beb596c3429b98ec5066
2021-01-13Workaround for Cortex N1 erratum 1946160johpow01
Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0, r2p0, r3p0, r3p1, r4p0, and r4p1. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present starting from r0p0 but this workaround applies to revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no workaround. SDEN can be found here: https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4
2021-01-13Workaround for Cortex A78 erratum 1951500johpow01
Cortex A78 erratum 1951500 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This workaround works on revisions r1p0 and r1p1, in r0p0 there is no workaround. SDEN can be found here: https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I47610cee75af6a127ea65edc4d5cffc7e6a2d0a3
2021-01-12Workaround for Cortex A78 erratum 1941498johpow01
Cortex A78 erratum 1941498 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1. The workaround is to set bit 8 in the ECTLR_EL1 register, there is a small performance cost (<0.5%) for setting this bit. SDEN can be found here: https://documentation-service.arm.com/static/5fb66157ca04df4095c1cc2e Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I959cee8e3d46c1b84ff5e4409ce5945e459cc6a9
2021-01-06AArch64: Fix assertions in processing dynamic relocationsAlexei Fedorov
This patch provides the following changes in fixup_gdt_reloc() function: - Fixes assertions in processing dynamic relocations, when relocation entries not matching R_AARCH64_RELATIVE type are found. Linker might generate entries of relocation type R_AARCH64_NONE (code 0), which should be ignored to make the code boot. Similar issue was fixed in OP-TEE (see optee_os/ldelf/ta_elf_rel.c commit 7a4dc765c133125428136a496a7644c6fec9b3c2) - Fixes bug when "b.ge" (signed greater than or equal) condition codes were used instead of "b.hs" (greater than or equal) for comparison of absolute addresses. - Adds optimisation which skips fixing Global Object Table (GOT) entries when offset value is 0. Change-Id: I35e34e055b7476843903859be947b883a1feb1b5 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-12-22PSCI: fix limit of 256 CPUs caused by cast to unsigned charGraeme Gregory
In psci_setup.c psci_init_pwr_domain_node() takes an unsigned char as node_idx which limits it to initialising only the first 256 CPUs. As the calling function does not check for a limit of 256 I think this is a bug so change the unsigned char to uint16_t and change the cast from the calling site in populate_power_domain_tree(). Also update the non_cpu_pwr_domain_node structure lock_index to uint16_t and update the function signature for psci_lock_init() appropriately. Finally add a define PSCI_MAX_CPUS_INDEX to psci_private.h and add a CASSERT to psci_setup.c to make sure PLATFORM_CORE_COUNT cannot exceed the index value. Signed-off-by: Graeme Gregory <graeme@nuviainc.com> Change-Id: I9e26842277db7483fd698b46bbac62aa86e71b45
2020-12-18Workaround for Cortex A76 erratum 1946160johpow01
Cortex A76 erratum 1946160 is a Cat B erratum, present in some revisions of the A76 processor core. The workaround is to insert a DMB ST before acquire atomic instructions without release semantics. This issue is present in revisions r0p0 - r4p1 but this workaround only applies to revisions r3p0 - r4p1, there is no workaround for older versions. SDEN can be found here: https://documentation-service.arm.com/static/5fbb77d7d77dd807b9a80cc1 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ief33779ee76a89ce2649812ae5214b86a139e327
2020-12-11Add support for FEAT_MTPMU for Armv8.6Javier Almansa Sobrino
If FEAT_PMUv3 is implemented and PMEVTYPER<n>(_EL0).MT bit is implemented as well, it is possible to control whether PMU counters take into account events happening on other threads. If FEAT_MTPMU is implemented, EL3 (or EL2) can override the MT bit leaving it to effective state of 0 regardless of any write to it. This patch introduces the DISABLE_MTPMU flag, which allows to diable multithread event count from EL3 (or EL2). The flag is disabled by default so the behavior is consistent with those architectures that do not implement FEAT_MTPMU. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: Iee3a8470ae8ba13316af1bd40c8d4aa86e0cb85e
2020-12-02Aarch64: Add support for FEAT_MTE3Alexei Fedorov
This patch provides the following changes: - Adds definition for FEAT_MTE3 value in ID_AA64PFR1_EL1 register - Enables Memory Tagging Extension for FEAT_MTE3. Change-Id: I735988575466fdc083892ec12c1aee89b5faa472 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-11-30Add support for Neoverse-N2 CPUs.Javier Almansa Sobrino
Enable basic support for Neoverse-N2 CPUs. Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com> Change-Id: I498adc2d9fc61ac6e1af8ece131039410872e8ad
2020-11-12Revert workaround for A77 erratum 1800714johpow01
This errata workaround did not work as intended and was revised in subsequent SDEN releases so we are reverting this change. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4686 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I8554c75d7217331c7effd781b5f7f49b781bbebe
2020-11-12Revert workaround for A76 erratum 1800710johpow01
This errata workaround did not work as intended and was revised in subsequent SDEN releases so we are reverting this change. This is the patch being reverted: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4684 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I560749a5b55e22fbe49d3f428a8b9545d6bdaaf0
2020-10-20lib: el3_runtime: Fix SPE system registers in el2_sysregs_contextArunachalam Ganapathy
Include EL2 registers related to SPE in EL2 context save/restore routines if architecture supports it and platform wants to use these features in Secure world. Change-Id: Ie01a2c38fa5f6c907276eddec120fdfb222561a6 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-20lib: el3_runtime: Conditionally save/restore EL2 NEVE registersArunachalam Ganapathy
Include EL2 registers related to Nested Virtualization in EL2 context save/restore routines if architecture supports it and platform wants to use these features in Secure world. Change-Id: If006ab83bbc2576488686f5ffdff88b91adced5c Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-20lib: el3_runtime: Fix aarch32 system registers in el2_sysregs_contextArunachalam Ganapathy
AArch64-only platforms do not implement AArch32 at EL1 and higher ELs. In such cases the build option CTX_INCLUDE_AARCH32_REGS is set to 0. So don't save/restore aarch32 system registers in el2_sysregs_context save/restore routines if CTX_INCLUDE_AARCH32_REGS is set to 0. Change-Id: I229cdd46136c4b4bc9623b02eb444d904e09ce5a Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
2020-10-18Merge "Increase type widths to satisfy width requirements" into integrationJoanna Farley
2020-10-16Merge changes Iba51bff1,I3f563cff into integrationMadhukar Pappireddy
* changes: plat:qti Mandate SMC implementaion and bug fix Update in coreboot_get_memory_type API to include size as well
2020-10-16Update in coreboot_get_memory_type API to include size as wellSaurabh Gorecha
Change-Id: I3f563cffd58b0591b433c85c0ff6b71e486eb2c8 Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org>
2020-10-14Merge "Don't return error information from console_flush" into integrationMark Dykes
2020-10-12Increase type widths to satisfy width requirementsJimmy Brisson
Usually, C has no problem up-converting types to larger bit sizes. MISRA rule 10.7 requires that you not do this, or be very explicit about this. This resolves the following required rule: bl1/aarch64/bl1_context_mgmt.c:81:[MISRA C-2012 Rule 10.7 (required)]<None> The width of the composite expression "0U | ((mode & 3U) << 2U) | 1U | 0x3c0U" (32 bits) is less that the right hand operand "18446744073709547519ULL" (64 bits). This also resolves MISRA defects such as: bl2/aarch64/bl2arch_setup.c:18:[MISRA C-2012 Rule 12.2 (required)] In the expression "3U << 20", shifting more than 7 bits, the number of bits in the essential type of the left expression, "3U", is not allowed. Further, MISRA requires that all shifts don't overflow. The definition of PAGE_SIZE was (1U << 12), and 1U is 8 bits. This caused about 50 issues. This fixes the violation by changing the definition to 1UL << 12. Since this uses 32bits, it should not create any issues for aarch32. This patch also contains a fix for a build failure in the sun50i_a64 platform. Specifically, these misra fixes removed a single and instruction, 92407e73 and x19, x19, #0xffffffff from the cm_setup_context function caused a relocation in psci_cpus_on_start to require a linker-generated stub. This increased the size of the .text section and caused an alignment later on to go over a page boundary and round up to the end of RAM before placing the .data section. This sectionn is of non-zero size and therefore causes a link error. The fix included in this reorders the functions during link time without changing their ording with respect to alignment. Change-Id: I76b4b662c3d262296728a8b9aab7a33b02087f16 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-10-09Don't return error information from console_flushJimmy Brisson
And from crash_console_flush. We ignore the error information return by console_flush in _every_ place where we call it, and casting the return type to void does not work around the MISRA violation that this causes. Instead, we collect the error information from the driver (to avoid changing that API), and don't return it to the caller. Change-Id: I1e35afe01764d5c8f0efd04f8949d333ffb688c1 Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
2020-10-07Workaround for Cortex A77 erratum 1925769johpow01
Cortex A77 erratum 1925769 is a Cat B erratum, present in older revisions of the Cortex A77 processor core. The workaround is to set bit 8 in the ECTLR_EL1 register, there is a small performance cost (<0.5%) for setting this bit. SDEN can be found here: https://documentation-service.arm.com/static/5f7c35d0d3be967f7be46d33 Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I9cf0e0b5dc1e3e32e24279d2632c759cc7bd7ce9
2020-10-06Merge changes from topics "rename-herculesae-a78ae", "rename-zeus-v1" into ↵Madhukar Pappireddy
integration * changes: Rename Neoverse Zeus to Neoverse V1 Rename Cortex Hercules AE to Cortex 78 AE
2020-10-05Merge "Workaround for Cortex A76 erratum 1868343" into integrationMadhukar Pappireddy
2020-10-05Rename Neoverse Zeus to Neoverse V1Jimmy Brisson
Change-Id: Ieb411e2f8092fa82062e619305b680673a8f184f Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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