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2021-10-19build(plat/marvell): do not print comments on stdoutPali Rohár
'#' needs to be before TAB, otherwise comment is printed on stdout during build. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I502374ef35d91e194dc35b78d31d6884a466fab2
2021-10-13build(plat/marvell): add descriptions why some checks are requiredPali Rohár
This change adds just comments why some checks are required. They check that ENV variables and external repos are correctly set for TF-A builds. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I2f8af5061411c0c92d3875917f4d97b60dc2cf10
2021-10-11plat/marvell/a8k: add Globalscale Mochabin supportRobert Marko
Add support for Globalscale MOCHAbin board. Its based on Armada 7040 SoC and ships in multiple DRAM options: * 2GB DDR4 (1CS) * 4GB DDR4 (1CS) * 8GB DDR4 (2CS) Since it ships in multiple DRAM configurations, an Armada 3k style DDR_TOPOLOGY variable is added. Currently, this only has effect on the MOCHAbin, but I expect more boards with multiple DRAM sizes to be supported. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Change-Id: I8a1ec9268fed34f6a81c5cbf1e891f638d461305
2021-10-05refactor(makefile): remove BL prefixes in build macrosZelalem Aweke
The current Makefile assumes all TF-A binaries have BL prefixes (BL1, BL2, etc). Now that we have other binary names with FEAT_RME feature, remove this assumption. With this change, we need to pass the full name of a binary when using build macros. Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com> Change-Id: I44e094b2366aa526f807d92dffa709390d14d145
2021-08-26feat(plat/marvell/a8k): allow overriding default pathsMarcin Wojtas
The common makefile used by every a8k/cn913x platform (a8k_common.mk) assumed default paths in PLAT_INCLUDES, BLE/BL31_PORTING_SOURCES. Allow overriding those variables, in order to avoid code duplication. It can be helpful in case using multiple board variants or sharing common settings between different platforms. Change-Id: Idce603e44ed04d99fb1e3e11a2bb395d552e2bf7 Signed-off-by: Marcin Wojtas <mw@semihalf.com>
2021-07-10fix(plat/marvell/a8k): Add missing build dependency for BLE targetPali Rohár
BLE source files depend on external Marvell mv-ddr-marvell tree (specified in $(MV_DDR_PATH) variable) and its header files. Add dependency on $(MV_DDR_LIB) target which checks that variable $(MV_DDR_PATH) is correctly set and ensures that make completes compilation of mv-ddr-marvell tree. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I73968b24c45d9af1e3500b8db7a24bb4eb2bfa47
2021-07-10fix(plat/marvell/a8k): Correctly set include directories for individual targetsPali Rohár
Do not set all include directories, including those for external targets in one PLAT_INCLUDES variable. Instead split them into variables: * $(PLAT_INCLUDES) for all TF-A BL images * BLE target specific $(PLAT_INCLUDES) only for Marvell BLE image * $(MV_DDR_INCLUDES) for targets in external Marvell mv-ddr-marvell tree Include directory $(CURDIR)/drivers/marvell is required by TF-A BL images, so move it from ble.mk to a8k_common.mk. Include directory $(MV_DDR_PATH) is needed only by Marvell BLE image, so move it into BLE target specific $(PLAT_INCLUDES) variable. And remaining include directories specified in ble.mk are needed only for building external dependences from Marvell mv-ddr tree, so move them into $(MV_DDR_INCLUDES) variable and correctly use it in $(MV_DDR_LIB) target. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I331f7de675dca2bc70733d56b768f00d56ae4a67
2021-07-10fix(plat/marvell/a8k): Require that MV_DDR_PATH is correctly setPali Rohár
Target mrvl_flash depends on external mv_ddr source code which is not part of TF-A project. Do not expect that it is pre-downloaded at some specific location and require user to specify correct path to mv_ddr source code via MV_DDR_PATH build option. TF-A code for Armada 37x0 platform also depends on mv_ddr source code and already requires passing correct MV_DDR_PATH build option. So for A8K implement same checks for validity of MV_DDR_PATH option as are already used by TF-A code for Armada 37x0 platform. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I792f2bfeab0cec89b1b64e88d7b2c456e22de43a
2021-06-01refactor(plat/marvell/uart): de-duplicate PLAT_MARVELL_UART macrosPali Rohár
Macros PLAT_MARVELL_BOOT_UART* and PLAT_MARVELL_CRASH_UART* are defined to same values. De-duplicate them into PLAT_MARVELL_UART* macros. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Iae5daf7cad6a971e6f3dbe561df3d0174106ca7f
2021-06-01refactor(plat/marvell/uart): remove unused macrosPali Rohár
Macros PLAT_MARVELL_BL31_RUN_UART* are not used since commit d7c4420cb8a7 ("plat/marvell: Migrate to multi-console API"). Remove them. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5ec959ef4de87dcfb332c017ad2599bf8af6ffc3
2021-04-20plat/marvell: a8k: move efuse definitions to separate headerKonstantin Porotchkin
Move efuse definitions to a separate header file for later usage with other FW modules. Change-Id: I2e9465f760d0388c8e5863bc64a4cdc57de2417f Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/47313 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Yi Guo <yi.guo@cavium.com>
2021-04-20plat/marvell/armada: postpone MSS CPU startup to BL31 stageKonstantin Porotchkin
Normally the CP MSS CPU was started at the end of FW load to IRAM at BL2. However, (especailly in secure boot mode), some bus attributes should be changed from defaults before the MSS CPU tries to access shared resources. This patch starts to use CP MSS SRAM for FW load in both secure and non-secure boot modes. The FW loader inserts a magic number into MSS SRAM as an indicator of successfully loaded FS during the BL2 stage and skips releasing the MSS CPU from the reset state. Then, at BL31 stage, the MSS CPU is released from reset following the call to cp110_init function that handles all the required bus attributes configurations. Change-Id: Idcf81cc350a086835abed365154051dd79f1ce2e Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46890 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com>
2021-04-20plat: marvell: armada: a8k: Fix LD selector maskGuo Yi
Fixed a bug that the actually bit number was used as a mask to select LD0 or LD1 fuse Signed-off-by: Guo Yi <yguo@cavium.com> Change-Id: I4bec268c3dc2566350b4a73f655bce222707e25b Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/46146 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2021-04-20plat/marvell/armada: allow builds without MSS supportKonstantin Porotchkin
Setting MSS_SUPPORT to 0 also removes requirement for SCP_BL2 definition. Images build with MSS_SUPPORT=0 will not include service CPUs FW and will not support PM, FC and other features implemented in these FW images. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: Idf301ebd218ce65a60f277f3876d0aeb6c72f105 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/37769 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
2021-04-20drivers: marvell: add support for secure read/write of dfx register-setGrzegorz Jaszczyk
Since the dfx register set is going to be marked as secure expose dfx secure read and write function via SiP services. In introduced misc_dfx driver some registers are white-listed so non-secure software can still access them. This will allow non-secure word drivers access some white-listed registers related to e.g.: Sample at reset, efuses, SoC type and revision ID accesses. Change-Id: If9ae2da51ab2e6ca62b9a2c940819259bf25edc0 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/25055 Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2021-04-20ddr_phy: use smc calls to access ddr phy registersAlex Leibovich
Added smc calls support to access ddr phy registers. Change-Id: Ibaa0a8e20b6398ab394c7e2e9ea61f9a28cdb870 Signed-off-by: Alex Leibovich <alexl@marvell.com> Reviewed-on: https://sj1git1.cavium.com/20791 Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2021-04-20drivers: marvell: add thermal sensor driver and expose it via SIP serviceGrzegorz Jaszczyk
Since the dfx register set is going to be marked as secure (in order to protect efuse registers for non secure access), accessing thermal registers which are part of dfx register set, will not be possible from lower exception levels. Due to above expose thermal driver as a SiP service. This will allow Linux and U-Boot thermal driver to initialise and perform various operations on thermal sensor. The thermal sensor driver is based on Linux drivers/thermal/armada_thermal.c. Change-Id: I4763a3bf5c43750c724c86b1dcadad3cb729e93e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/20581 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2021-02-25plat/marvell: cn913x: allow CP1/CP2 mapping at BLE stageKonstantin Porotchkin
Map IO WIN to CP1 and CP2 at all stages including the BLE. Do not map CP1/CP2 if CP_NUM is lower than 2 and 3 accordingly. This patch allows access to CP1/CP2 internal registers at BLE stage if CP1/CP2 are connected. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: Icf9ffdf2e9e3cdc2a153429ffd914cc0005f9eca Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/36939 Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Yi Guo <yi.guo@cavium.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com>
2021-02-24plat/marvell/armada/common/mss: use MSS SRAM in secure modeKonstantin Porotchkin
The CP MSS IRAM is only accessible by CM3 CPU and MSS DMA. In secure boot mode the MSS DMA is unable to directly load the MSS FW image from DRAM to IRAM. This patch adds support for using the MSS SRAM as intermediate storage. The MSS FW image is loaded by application CPU into the MSS SRAM first, then transferred to MSS IRAM by MSS DMA. Such change allows the CP MSS image load in secure mode. Change-Id: Iee7a51d157743a0bdf8acb668ee3d599f760a712 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaszczyk@marvell.com>
2021-02-11plat/marvell/armada/a8k: support HW RNG by SMCKonstantin Porotchkin
Add initialization for TRNG-IP-76 driver and support SMC call 0xC200FF11 used for reading HW RNG value by secondary bootloader software for KASLR support. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Change-Id: I1d644f67457b28d347523f8a7bfc4eacc45cba68 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/atf/+/32688 Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Ofer Heifetz <oferh@marvell.com>
2021-01-29plat: marvell: armada: Show informative build messages and blank linesPali Rohár
Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Ibc15db07c581eca29c1b1fbfb145cee50dc42605
2021-01-29plat: marvell: armada: Move definition of mrvl_flash target to common ↵Pali Rohár
marvell_common.mk file Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: If545b3812787cc97b95dbd61ed51c37d30c5d412
2021-01-07Makefile: Do not mark file targets as .PHONY targetPali Rohár
Only non-file targets should be set a .PHONY. Otherwise if file target is set as .PHONY then targets which depends on those file .PHONY targets would be always rebuilt even when their prerequisites are not changed. File target which needs to be always rebuilt can be specified in Make system via having a prerequisite on some .PHONY target, instead of marking whole target as .PHONY. In Makefile projects it is common to create empty .PHONY target named FORCE for this purpose. This patch changes all file targets which are set as .PHONY to depends on new .PHONY target FORCE, to ensure that these file targets are always rebuilt (as before). Basically they are those targets which calls external make subprocess. After FORCE target is specified in main Makefile, remove it from other Makefile files to prevent duplicate definitions. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Iee3b4e0de93879b95eb29a1745a041538412e69e
2020-12-07plat: marvell: armada: Add missing FORCE, .PHONY and clean targetsPali Rohár
FORCE target is used as a dependency for other file targets which needs to be always rebuilt. .PHONY target is standard Makefile target which specify non-file targets and therefore needs to be always rebuilt. Targets clean, realclean and distclean are .PHONY targets used to remove built files. Correctly set that mrvl_clean target is prerequisite for these clean targets to ensure that built files are removed. Finally this change with usage of FORCE target allows to remove mrvl_clean hack from the prerequisites of a8k ${DOIMAGETOOL} target which was used just to ensure that ${DOIMAGETOOL} is always rebuilt via make subprocess. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I2fa8971244b43f101d846fc433ef7b0b6f139c92
2020-11-19plat: marvell: armada: Add new target mrvl_bootimagePali Rohár
This new target builds boot-image.bin binary as described in documentation. This image does not contain WTMI image and therefore WTP repository is not required for building. Having ability to build just this boot-image.bin binary without full flash-image.bin is useful for A3720 Turris MOX board which does not use Marvell's WTP and a3700_utils. To reduce duplicity between a8k and a3k code, define this new target and also definitions for $(BUILD_PLAT)/$(BOOT_IMAGE) in common include file marvell_common.mk. For this purpose it is needed to include plat/marvell/marvell.mk file from a3700_common.mk unconditionally (and not only when WTP is defined). Now when common file plat/marvell/marvell.mk does not contain definition for building $(DOIMAGETOOL), it is possible to move its inclusion at the top of the a3700_common.mk file. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Ic58303b37a1601be9a06ff83b7a279cb7cfc8280
2020-10-21plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8kPali Rohár
Currently a3k target is misusing ${DOIMAGETOOL} target for building flash and UART images. It is not used for building image tool. So move ${DOIMAGETOOL} target from common marvell include file into a8k include file and add correct invocation of ${MAKE} into a3k for building flash and UART images. Part of this change is also checks that MV_DDR_PATH for a3k was specified by user as this option is required for building a3k flash and UART images. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5ae9d08b8505460933f17836c9b6435fd6e51bb6
2020-10-19plat: marvell: armada: Fix including plat/marvell/marvell.mk filePali Rohár
Include file plat/marvell/marvell.mk for platform A3700 was included two times. Once from file plat/marvell/armada/a3k/common/a3700_common.mk and second time from common file plat/marvell/armada/common/marvell_common.mk. It caused following warning every time was make called: plat/marvell/marvell.mk:51: warning: overriding recipe for target 'mrvl_clean' plat/marvell/marvell.mk:51: warning: ignoring old recipe for target 'mrvl_clean' Change in this commit removes inclusion of plat/marvell/marvell.mk file in common file plat/marvell/armada/common/marvell_common.mk. As a80x0 platform needs this include file, add it also into a80x0 platform specific include file lat/marvell/armada/a8k/common/a8k_common.mk. Also moves inclusion of plat/marvell/marvell.mk file in a3700 platform file plat/marvell/armada/a3k/common/a3700_common.mk at correct place. Global plat/marvell/marvell.mk expects that variables DOIMAGEPATH and DOIMAGETOOL are already defined, but it defines MARVELL_SECURE_BOOT variable which is needed by plat/marvell/armada/a3k/common/a3700_common.mk. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5cbbd7eb8a3376924419f9850516b2a4924be5aa
2020-10-04plat: marvell: ap806: implement workaround for errata-id FE-4265711Stefan Chulski
ERRATA ID: FE-4265711 - Incorrect CNTVAL reading CNTVAL reflects the global system counter value in binary format. Due to this erratum, the CNTVAL value presented to the processor may be incorrect for several clock cycles. Workaround: Override the default value of AP Register Device General control 20 [19:16] and AP Register Device General Control 21 [11:8] to the value of 0x3. Change-Id: I1705608d08acd9631ab98d6f7ceada34d6b8336f Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
2020-08-10Merge changes from topic "release/14.0" into integrationManish Pandey
* changes: docs: marvell: update PHY porting layer description docs: marvell: update path in marvell documentation docs: marvell: update build instructions with CN913x plat: marvell: octeontx: add support for t9130 plat: marvell: t9130: add SVC support plat: marvell: t9130: update AVS settings plat: marvell: t9130: pass actual CP count for load_image plat: marvell: armada: a7k: add support to SVC validation mode plat: marvell: armada: add support for twin-die combined memory device
2020-08-04Use abspath to dereference $BUILD_BASEGrant Likely
If the user tries to change BUILD_BASE to put the build products outside the build tree the compile will fail due to hard coded assumptions that $BUILD_BASE is a relative path. Fix by using $(abspath $(BUILD_BASE)) to rationalize to an absolute path every time and remove the relative path assumptions. This patch also adds documentation that BUILD_BASE can be specified by the user. Signed-off-by: Grant Likely <grant.likely@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ib1af874de658484aaffc672f30029b852d2489c8
2020-07-30plat: marvell: t9130: add SVC supportAlex Evraev
As the preparation for adding the CN913x SoC family support introduce code that enable SVC and the frequency handling specific for the AP807 North Bridge. Change-Id: Ibe34a511b49cd9671a2e53b77bdcfc644bb915e3 Signed-off-by: Alex Evraev <alexev@marvell.com>
2020-07-30plat: marvell: t9130: update AVS settingsGrzegorz Jaszczyk
Update AVS settings and remove unused macros. This is a preparation patch for adding CN913x SoC family support. Change-Id: Ib1dd70885a316ed5763d0f4730d0e4734da117b7 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2020-07-30plat: marvell: t9130: pass actual CP count for load_imageBen Peled
Add CN913x case to bl2_plat_get_cp_count. Fix loading of cp1/2 image. This is a preparation patch for adding CN913x SoC family support. Change-Id: Id84a30203d20572fc0dfd3f91ea395c199a85fe9 Signed-off-by: Ben Peled <bpeled@marvell.com>
2020-07-30plat: marvell: armada: a7k: add support to SVC validation modeAlex Evraev
Add support for “AVS reduction” feature at this mode for 7040 Dual Cluster operation mode at CPU=1600MHz Change-Id: Ia72b10e0ccfad07568bf4c089ea3990173ae24b2 Signed-off-by: Alex Evraev <alexev@marvell.com>
2020-07-21Merge changes I0826ef8b,I9b4659a1 into integrationManish Pandey
* changes: plat: marvell: armada: a8k: Add support for iEi Puzzle-M801 board plat: marvell: armada: a8k: common: Fix a8k_common.mk to use BOARD_DIR variable
2020-07-10plat: marvell: armada: a8k: change CCU LLC SRAM mappingKonstantin Porotchkin
The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage. The CCU have to prepare SRAM window, but point to the DRAM-0 target until the SRAM is actually enabled. This patch changes CCU SRAM window target to DRAM-0 Remove dependence between LLC_SRAM and LLC_ENABLE and update the build documentation. The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000) Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2020-07-10plat: marvell: armada: adjust trusted DRAM size to match OP-TEE OSKonstantin Porotchkin
Area used as trusted DRAM is 12MB in Marvell OP-TEE OS module. It is followed by 4MB of shared memory. Change-Id: If8edeeec5861b529408baca25f78c06a0a440d8c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2020-07-10drivers: marvell: mg_conf_cm3: add basic driverGrzegorz Jaszczyk
Implement function which will allow to start AP FW. Change-Id: Ie0fc8ad138bf56b10809cdc92d1e5e96a2aaf33f Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2020-07-03plat: marvell: armada: a8k: common: Fix a8k_common.mk to use BOARD_DIR variableLuka Kovacic
Use the BOARD_DIR variable instead of PLAT_FAMILY_BASE variable for determening the path of the system_power.c file. The variable was not updated, when it was deprecated in a8k_common.mk in commit 613bbde09e48874658af5a00612fe2a0b0388523. Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr> Change-Id: I9b4659a19ba3cd5c869d44c5d834b220f49136e8
2020-06-19plat: marvell: armada: a8k: add OP-TEE OS MMU tablesKonstantin Porotchkin
Adjust the latest OP-TEE memory definitions to the newest TF-A baseline. Change-Id: Ib9c82b85f868adaf3c7285eb340486bda9c59c36 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2020-06-19plat: marvell: armada: reduce memory size reserved for FIP imageMarcin Wojtas
It is not needed to reserve 64MB for FIP. Limit this to 4MB for both supported Armada SoC families. Change-Id: I58a8ce4408a646fe1afd3c1ea1ed54007c8d205d Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [Extract from bigger commit] Signed-off-by: Marcin Wojtas <mw@semihalf.com>
2020-06-19plat: marvell: armada: platform definitions cleanupKonstantin Porotchkin
- Remove TRUSTED_DRAM_BASE TRUSTED_DRAM_SIZE MARVELL_TRUSTED_SRAM_BASE - Rename PLAT_MARVELL_TRUSTED_DRAM_* -> PLAT_MARVELL_TRUSTED_RAM_* PLAT_MARVELL_TRUSTED_SRAM_* -> MARVELL_TRUSTED_DRAM_* MARVELL_MAP_SHARED_RAM -> MARVELL_MAP_SECURE_RAM - Move MARVELL_TRUSTED_DRAM_SIZE to marvell_def.h - Enable MARVELL_MAP_SECURE_RAM region in BL2U memory map - Add dependency of MARVELL_MAP_SHARED_RAM on LLC_SRAM - Add minor style improvents Change-Id: Iebc03361e4f88489af1597f54e137b27c241814c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> [Improve patch after rebase] Signed-off-by: Marcin Wojtas <mw@semihalf.com>
2020-06-19plat: marvell: armada: a8k: check CCU window state before loading MSS BL2Konstantin Porotchkin
Make sure the current CCU window is not in use before adding a new address map during MSS BL2 image load preparations. At BL2 stage the CCU Win-2 points to DRAM. If additional mapping is added to MSS BL2 stage initialization, the DDR entry will be destroyed and lead to the system hang. Change-Id: I215e83508acc37d54dab6954d791b9a74cc883ca Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2020-06-19plat: marvell: a8k: move address config of cp1/2 to BL2Ben Peled
The configuration space of each standalone CP was updated in BL31. Loading FW procedure take places earlier in SCP_BL2. It needs to be done after access to each CP is provided. Moving the proper configuration from BL31 to BL2 solves it. Change-Id: I44cf88dfd4ebf09130544332bfdd3d16ef2674ea Signed-off-by: Ben Peled <bpeled@marvell.com>
2020-06-19plat: marvell: armada: re-enable BL32_BASE definitionKonstantin Porotchkin
As a preparation to support proper loading the OPTEE OS image, enable the BL32 specific defines in case the SPD is used. On the occasion move two BL32-related macros to marvell_def.h and fix BL32_LIMIT definition. Change-Id: Id4e2d81833bc1895650cca8b0fc0bfc341cf77f3 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
2020-06-19plat: marvell: a8k: extend includes to take advantage of the phy_porting_layerGrzegorz Jaszczyk
The phy porting layer uses defaults defined in "phy-default-porting-layer.h" when board specific file "phy-porting-layer.h" is not found. Because of the regression the board specific directory was not included, therefore all boards used default parameters. Change-Id: I66e5e6eb8a39cca5aeeb4de6dab2ceddc39c1e31 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2020-06-19plat: marvell: armada: configure amb for all CPsGrzegorz Jaszczyk
Before this patch the configuration took place only for CP0 and CP1, but since new platforms can contains up to 3 CPs update is required. Change-Id: Iebd50bbe7b9772063e2c4efb3a7ecbfd593e950d Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2020-06-07ble: ap807: clean-up PLL configuration sequenceAlex Leibovich
Remove pll powerdown from pll configuration sequence to improve stability. Remove redundant cases, which no longer exist. Also get rid of irrelevant definition of CPU_2200_DDR_1200_RCLK_1200, which is not used by 806/807. Change-Id: If911e7dee003dfb9a42fafd7ffe34662f026fd23 Signed-off-by: Alex Leibovich <alexl@marvell.com>
2020-06-07plat: marvell: mci: perform mci link tuning for all mci interfacesGrzegorz Jaszczyk
This commit introduces two changes: - remove hardcoded references to mci0 from the driver - perform mci optimization for all mci interfaces It fixes performance issues observed on cn9132 CP2. Change-Id: I4e040cd54ff95c9134035ac89b87d8feb28e9eba Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
2020-06-07plat: marvell: mci: use more meaningful name for mci link tuningGrzegorz Jaszczyk
The mci_initialize function name was misleading. The function itself doesn't initialize MCI in general but performs MCI link tuning for performance improvement. Change-Id: I13094ad2235182a14984035bbe58013ebde84a7e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
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