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2021-09-10Merge remote-tracking branch 'aosp/upstream-master' into HEADAlistair Delva
Change-Id: I1297535c4cd8b3e8cae06c9d43535fbe1416fce3
2021-09-04Merge "feat(board/rdn2): add tzc master source ids for soc dma" into integrationMadhukar Pappireddy
2021-09-03Merge changes I3c20611a,Ib1671011,I5eab3f33,Ib149b3ea into integrationMadhukar Pappireddy
* changes: refactor(plat/nxp): refine api to read SVR register refactor(plat/nxp): each errata use a seperate source file refactor(plat/nxp): use a unified errata api refactor(plat/soc-lx2160): move errata to common directory
2021-08-26refactor(plat/nxp): refine api to read SVR registerJiafei Pan
1. Refined struct soc_info_t definition. 2. Refined get_soc_info function. 3. Fixed some SVR persernality value. 4. Refined API to get cluster numbers and cores per cluster. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I3c20611a523516cc63330dce4c925e6cda1e93c4
2021-08-26feat(plat/marvell): introduce t9130_cex7_evalMarcin Wojtas
This patch adds the necessary files to support the SolidRun CN913X CEx7 Evaluation Board. Because the DRAM connectivity and SerDes settings is shared with the CN913X DB - reuse relevant board-specific files. Change-Id: I75a4554a4373953ca3fdf3b04c4a29c2c4f8ea80 Signed-off-by: Marcin Wojtas <mw@semihalf.com>
2021-08-26feat(plat/marvell/a8k): allow overriding default pathsMarcin Wojtas
The common makefile used by every a8k/cn913x platform (a8k_common.mk) assumed default paths in PLAT_INCLUDES, BLE/BL31_PORTING_SOURCES. Allow overriding those variables, in order to avoid code duplication. It can be helpful in case using multiple board variants or sharing common settings between different platforms. Change-Id: Idce603e44ed04d99fb1e3e11a2bb395d552e2bf7 Signed-off-by: Marcin Wojtas <mw@semihalf.com>
2021-08-25Merge changes from topic "allwinner-r329" into integrationAndré Przywara
* changes: feat(plat/allwinner): add R329 support refactor(plat/allwinner): allow custom BL31 offset refactor(plat/allwinner): allow new AA64nAA32 position fix(plat/allwinner): delay after enabling CPU power
2021-08-25Merge "cpu: add support for Demeter CPU" into integrationJoanna Farley
2021-08-25refactor(plat/nxp): each errata use a seperate source fileJiafei Pan
Don't mix erratas together in one file. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Ib1671011b91a41b0653210e4706d62b7e946c642
2021-08-25refactor(plat/nxp): use a unified errata apiJiafei Pan
Use a unfied API soc_errata() for each platforms, add print a INFO message for each enabled errata, so that it will be easy to check which errata is enabled on current platform. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: I5eab3f338db6b46c57cbad475819043fc60ca6d3
2021-08-25refactor(plat/soc-lx2160): move errata to common directoryJiafei Pan
Will add more Erratas, some errata can be used for multiple platforms, so move errata to be common code which can be share between different platforms. Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com> Change-Id: Ib149b3eac365bdb593331e9f38f0b89d92c9c0d1
2021-08-25feat(plat/allwinner): add R329 supportIcenowy Zheng
Allwinner R329 is a new dual-core Corte-A53 SoC. Add basical TF-A support for it, to provide a PSCI implementation containing CPU boot/shutdown and SoC reset. Change-Id: I0fa37ee9b4a8e0e1137bf7cf7d614b6ca9624bfe Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
2021-08-25refactor(plat/allwinner): allow custom BL31 offsetIcenowy Zheng
Not all Allwinner SoCs have the same arrangement to SRAM A2. Allow to specify a offset at which BL31 will stay in SRAM A2. Change-Id: I574140ffd704a796fae0a5c2d0976e85c7fcbdf9 Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
2021-08-25refactor(plat/allwinner): allow new AA64nAA32 positionIcenowy Zheng
In newer Allwiner SoCs, the AA64nAA32 wires are mapped to a new register called "General Control Register0" in the manual rather than the "Cluster 0 Control Register0" in older SoCs. Now the position of AA64nAA32 (reg and bit offset) is defined in a few macros instead assumed to be at bit offset 24 of SUNXI_CPUCFG_CLS_CTRL_REG0. Change-Id: I933d00b9a914bf7103e3a9dadbc6d7be1a409668 Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
2021-08-25fix(plat/allwinner): delay after enabling CPU powerIcenowy Zheng
Adds a 1us delay after enabling power to a CPU core, to prevent inrush-caused CPU crash before it's up. Change-Id: I8f4c1b0dc0d1d976b31ddc30efe7a77a1619b1b3 Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
2021-08-24Merge "fix(rpi4): drop /memreserve/ region" into integrationAndré Przywara
2021-08-24feat(board/rdn2): add tzc master source ids for soc dmaVijayenthiran Subramaniam
Add TZC master source id for DMA in the SoC space and for the DMAs behind the I/O Virtualization block to allow the non-secure transactions from these DMAs targeting DRAM. Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Change-Id: I77a2947b01b4b49a7c1940f09cf62b7b5257657c
2021-08-20Merge changes I976aef15,I11ae679f into integrationMadhukar Pappireddy
* changes: feat(plat/xilinx/zynqmp): add support for runtime feature config feat(plat/xilinx/zynqmp): sync IOCTL IDs
2021-08-20Merge "fix(plat/qemu): (NS_DRAM0_BASE + NS_DRAM0_SIZE) ADDR overflow 32bit" ↵Madhukar Pappireddy
into integration
2021-08-20Merge "fix(plat/st): apply security at the end of BL2" into integrationMadhukar Pappireddy
2021-08-19Merge "fix(plat/arm_fpga): enable AMU extension" into integrationAndré Przywara
2021-08-18feat(plat/xilinx/zynqmp): add support for runtime feature configRonak Jain
Add support for runtime feature configuration which are running on the firmware. Add new IOCTL IDs like IOCTL_SET_FEATURE_CONFIG and IOCTL_GET_FEATURE_CONFIG for configuring the features. Signed-off-by: Ronak Jain <ronak.jain@xilinx.com> Change-Id: I976aef15932783a25396b2adeb4c8f140cc87e79
2021-08-18feat(plat/xilinx/zynqmp): sync IOCTL IDsRonak Jain
Sync IOCTL IDs in order to avoid conflict with other components like, Linux and firmware. Hence assigning value to IDs to make it more specific. Signed-off-by: Ronak Jain <ronak.jain@xilinx.com> Change-Id: I11ae679fbd0a953290306b62d661cc142f50dc28
2021-08-18fix(plat/qemu): (NS_DRAM0_BASE + NS_DRAM0_SIZE) ADDR overflow 32bitlwpDarren
after this commit: If15cf3b9d3e2e7876c40ce888f22e887893fe696 plat/qemu/common/qemu_pm.c:116: (entrypoint < (NS_DRAM0_BASE + NS_DRAM0_SIZE))) the above line (NS_DRAM0_BASE + NS_DRAM0_SIZE) = 0x100000000, which will overflow 32bit and cause ERROR SO add ULL to fix it tested on compiler: gcc version 10.2.1 20201103 (GNU Toolchain for the A-profile Architecture 10.2-2020.11 (arm-10.16)) Signed-off-by: Darren Liang <lwp513@qq.com> Change-Id: I1d769b0803142d37bd2968d765ab04a9c7c5c21a
2021-08-18Merge "feat: enabling stack protector for diphda" into integrationMadhukar Pappireddy
2021-08-17cpu: add support for Demeter CPUjohpow01
This patch adds the basic CPU library code to support the Demeter CPU. This CPU is based on the Makalu-ELP core so that CPU lib code was adapted to create this patch. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ib5740b748008a72788c557f0654d8d5e9ec0bb7f
2021-08-17fix(plat/arm_fpga): enable AMU extensionTom Cosgrove
As done recently for plat/tc0 in b5863cab9, enable AMU explicitly. This is necessary as the recent changes that enable SVE for the secure world disable AMU by default in the CPTR_EL3 reset value. Change-Id: Ie3abf1dee8a4e1c8c39f934da8e32d67891f5f09 Signed-off-by: Tom Cosgrove <tom.cosgrove@arm.com>
2021-08-17fix(plat/st): apply security at the end of BL2Yann Gautier
Now that the DDR is mapped secured, the security settings (TZC400 firewall) have to be applied at the end of BL2 for the OP-TEE case. This is required to avoid checskum computation error on U-Boot binary, for which MMU and TZC400 would not be aligned. Change-Id: I4a364f7117960e8fae1b579f341b9f140b766ea6 Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
2021-08-16refactor(tegra132): deprecate platformVarun Wadekar
The Tegra132 platforms have reached their end of life and are no longer used in the field. Internally and externally, all known programs have removed support for this legacy platform. This change removes this platform from the Tegra tree as a result. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I72edb689293e23b63290cdcaef60468b90687a5a
2021-08-16fix(rpi4): drop /memreserve/ regionAndre Przywara
Most DTBs used on the RaspberryPi contain a FDT /memreserve/ region, that covers the original secondaries' spin table. We need to reserve more memory than described there, to cover the whole of the TF-A image, so we add a /reserved-memory node to the DTB. However having the same memory region described by both methods upsets the Linux kernel and U-Boot, so we have to make sure there is only one instance describing this reserved memory. Keep our currently used /reserved-memory node, since it's more capable (it allows to mark the region as secure memory). Add some code to drop the original /memreserve/ region, since we don't need this anymore, because we take the secondaries out of their original spin loop. We explicitly check for the currently used size of 4KB for this region, to be alerted by any changes to this region in the upstream DTB. Change-Id: Ia3105560deb3f939e026f6ed715a9bbe68b56230 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-08-16Merge "refactor(plat/ea_handler): Use default ea handler implementation for ↵Madhukar Pappireddy
panic" into integration
2021-08-13Merge "feat(plat/versal): add support for SLS mitigation" into integrationMadhukar Pappireddy
2021-08-13refactor(plat/ea_handler): Use default ea handler implementation for panicPali Rohár
Put default ea handler implementation into function plat_default_ea_handler() which just print verbose information and panic, so it can be called also from overwritten / weak function plat_ea_handler() implementation. Replace every custom implementation of printing verbose error message of external aborts in custom plat_ea_handler() functions by a common implementation from plat_default_ea_handler() function. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I15897f61b62b4c3c29351e693f51d4df381f3b98
2021-08-13Merge changes Id93c4573,Ib7fea862,I44b9e5a9,I9e0ef734,I94d550ce, ... into ↵Joanna Farley
integration * changes: feat(plat/rcar3): emit RPC status to DT fragment if RPC unlocked feat(plat/rcar3): add a DRAM size setting for M3N feat(plat/rcar3): update IPL and Secure Monitor Rev.3.0.0 feat(plat/rcar3): add new board revision for Salvator-XS/H3ULCB feat(drivers/rcar3): ddr: add function to judge a DDR rank fix(drivers/rcar3): ddr: update DDR setting for H3, M3, M3N fix(drivers/rcar3): i2c_dvfs: fix I2C operation fix(drivers/rcar3): fix CPG registers redefinition fix(drivers/rcar3): emmc: remove CPG_CPGWPR redefinition fix(plat/rcar3): generate two memory nodes for larger than 2 GiB channel 0 refactor(plat/rcar3): factor out DT memory node generation feat(plat/rcar3): add optional support for gzip-compressed BL33
2021-08-13Merge changes from topic "st_fip_fconf" into integrationManish Pandey
* changes: feat(io_mtd): offset management for FIP usage feat(nand): count bad blocks before a given offset feat(plat/st): add helper to save boot interface fix(plat/st): improve DDR get size function refactor(plat/st): map DDR secure at boot refactor(plat/st): rework TZC400 configuration
2021-08-12feat: enabling stack protector for diphdaAbdellatif El Khlifi
This commit activates the stack protector feature for the diphda platform. Change-Id: Ib16b74871c62b67e593a76ecc12cd3634d212614 Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
2021-08-12Merge "feat(plat/imx/imx8m/imx8mm): enlarge BL33 (U-boot) size in FIP" into ↵Madhukar Pappireddy
integration
2021-08-11feat(plat/arm): Introduce TC1 platformUsama Arif
This renames tc0 platform folder and files to tc, and introduces TARGET_PLATFORM variable to account for the differences between TC0 and TC1. Signed-off-by: Usama Arif <usama.arif@arm.com> Change-Id: I5b4a83f3453afd12542267091b3edab4c139c5cd
2021-08-11Merge "feat(plat/mdeiatek/mt8192): add DFD control in SiP service" into ↵Madhukar Pappireddy
integration
2021-08-10Merge "revert(plat/xilinx): add timeout while waiting for IPI Ack" into ↵Madhukar Pappireddy
integration
2021-08-10Merge "feat(ff-a): update FF-A version to v1.1" into integrationOlivier Deprez
2021-08-09revert(plat/xilinx): add timeout while waiting for IPI AckVenkatesh Yadav Abbarapu
This reverts commit 4d9b9b2352f9a67849faf2d4484f5fcdd2788b01. Timeout in IPI ack was added for functional safety reason. Functional safety is not criteria for ATF. However, this creates issues for APIs that take long or non-deterministic duration like FPGA load. So revert this patch for now to fix FPGA loading issue. Need to add support for non-blocking API for FPGA loading with callback when API completes. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@xilinx.com> Change-Id: I940e798f1e2f7d0dfca1da5caaf8b94036d440c6
2021-08-10feat(plat/mdeiatek/mt8192): add DFD control in SiP serviceRex-BC Chen
DFD (Design for Debug) is a debugging tool, which scans flip-flops and dumps to internal RAM on the WDT reset. After system reboots, those values could be showed for debugging. Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I9c7af9a4f75216ed2c6b44458d121a352bef4b95
2021-08-06fix: avoid redefinition of 'efi_guid' structureManish V Badarkhe
Fixed the build error by removing the local definition of 'efi_guid' structure in 'sgi_ras.c' file as this structure definition is already populated in 'sgi_ras.c' file via 'uuid.h' header. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: I57687336863f2a0761c09b6c1aa00b4aa82a6a12
2021-08-06feat(ff-a): update FF-A version to v1.1J-Alves
Bump the required FF-A version in framework and manifests to v1.1 as upstream feature development goes. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I89b2bd3828a13fc4344ccd53bc3ac9c0c22ab29f
2021-08-02Merge changes from topic "fw-update-2" into integrationMadhukar Pappireddy
* changes: feat(sw_crc32): add software CRC32 support refactor(hw_crc32): renamed hw_crc32 to tf_crc32 feat(fwu): avoid booting with an alternate boot source docs(fwu): add firmware update documentation feat(fwu): avoid NV counter upgrade in trial run state feat(plat/arm): add FWU support in Arm platforms feat(fwu): initialize FWU driver in BL2 feat(fwu): add FWU driver feat(fwu): introduce FWU platform-specific functions declarations docs(fwu_metadata): add FWU metadata build options feat(fwu_metadata): add FWU metadata header and build options
2021-08-02refactor(hw_crc32): renamed hw_crc32 to tf_crc32Manish V Badarkhe
Renamed hw_crc32 to tf_crc32 to make the file and function name more generic so that the same name can be used in upcoming software CRC32 implementation. Change-Id: Idff8f70c50ca700a4328a27b49d5e1f14d2095eb Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-02feat(plat/arm): add FWU support in Arm platformsManish V Badarkhe
Added firmware update support in Arm platforms by using FWU platform hooks and compiling FWU driver in BL2 component. Change-Id: I71af06c09d95c2c58e3fd766c4a61c5652637151 Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
2021-08-02Merge "feat(ff-a): change manifest messaging method" into integrationOlivier Deprez
2021-07-30Merge changes Ic7579b60,I05414ca1 into integrationMadhukar Pappireddy
* changes: fix(plat/ea_handler): print newline before fatal abort error message feat(common/debug): add new macro ERROR_NL() to print just a newline
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-30 05:39:12 +0000