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2020-02-06Merge '5f62213e684dbea03b5a2bb732405a03ccc1a815' into masterAlistair Delva
Update to fix an incompatibility with U-Boot 2020.01 on rockpi IGNORE_MERGE_CONFLICT_CHECK==false positive Bug: 147107640 Change-Id: Ie767196449b0a8e661883f8220ae02eb3535c4a5
2020-02-03Merge "FDT wrappers: add functions for read/write bytes" into integrationManish Pandey
2020-02-03FDT wrappers: add functions for read/write bytesAlexei Fedorov
This patch adds 'fdtw_read_bytes' and 'fdtw_write_inplace_bytes' functions for read/write array of bytes from/to a given property. It also adds 'fdt_setprop_inplace_namelen_partial' to jmptbl.i files for builds with USE_ROMLIB=1 option. Change-Id: Ied7b5c8b38a0e21d508aa7bcf5893e656028b14d Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2020-01-30Merge "Use correct type when reading SCR register" into integrationAlexei Fedorov
2020-01-30Merge changes from topic "sb/select-cot" into integrationSandrine Bailleux
* changes: Introduce COT build option cert_create: Remove references to TBBR in common code cert_create: Introduce COT build option cert_create: Introduce TBBR CoT makefile
2020-01-29Introduce COT build optionSandrine Bailleux
Allows to select the chain of trust to use when the Trusted Boot feature is enabled. This affects both the cert_create tool and the firmware itself. Right now, the only available CoT is TBBR. Change-Id: I7ab54e66508a1416cb3fcd3dfb0f055696763b3d Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2020-01-29qemu: Implement PSCI_CPU_OFF.Andrew Walbran
This is based on the rpi implementation from https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/2746. Signed-off-by: Andrew Walbran <qwandor@google.com> Change-Id: I5fe324fcd9d5e232091e01267ea12147c46bc9c1
2020-01-29Merge changes I0fb7cf79,Ia8eb4710 into integrationSoby Mathew
* changes: qemu: Implement qemu_system_off via semihosting. qemu: Support ARM_LINUX_KERNEL_AS_BL33 to pass FDT address.
2020-01-28Enable -Wredundant-decls warning checkMadhukar Pappireddy
This flag warns if anything is declared more than once in the same scope, even in cases where multiple declaration is valid and changes nothing. Consequently, this patch also fixes the issues reported by this flag. Consider the following two lines of code from two different source files(bl_common.h and bl31_plat_setup.c): IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE); The IMPORT_SYM macro which actually imports a linker symbol as a C expression. The macro defines the __RO_START__ as an extern variable twice, one for each instance. __RO_START__ symbol is defined by the linker script to mark the start of the Read-Only area of the memory map. Essentially, the platform code redefines the linker symbol with a different (relevant) name rather than using the standard symbol. A simple solution to fix this issue in the platform code for redundant declarations warning is to remove the second IMPORT_SYM and replace it with following assignment static const unsigned long BL2_RO_BASE = BL_CODE_BASE; Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2020-01-28Use correct type when reading SCR registerLouis Mayencourt
The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2020-01-28Merge changes from topic "ti-cluster-power" into integrationSoby Mathew
* changes: ti: k3: drivers: ti_sci: Put sequence number in coherent memory ti: k3: drivers: ti_sci: Remove indirect structure of const data ti: k3: common: Enable ARM cluster power down ti: k3: common: Rename device IDs to be more consistent
2020-01-28Merge "plat/arm/sgi: move topology information to board folder" into integrationManish Pandey
2020-01-28Tegra194: enable spe-console functionalityVarun Wadekar
This patch enables the config to switch to the console provided by the SPE firmware. Change-Id: I5a3bed09ee1e84f958d0925501d1a79fb7f694de Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-01-27ti: k3: drivers: ti_sci: Put sequence number in coherent memoryAndrew F. Davis
The current message sequence number is accessed both with caches on and off so put this memory in the un-cached coherent section so accesses are consistent and coherency is maintained. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Ieeefefeaffc691e4e4c4de7c74490d50ff9de807
2020-01-27ti: k3: drivers: ti_sci: Remove indirect structure of const dataAndrew F. Davis
The 'info' structure contained what is only static data for this implementation of TI-SCI. Remove this indirection and remove the struct. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I2328fddf388bf7d56a56bd673c080e78c86fe072
2020-01-27ti: k3: common: Enable ARM cluster power downAndrew F. Davis
When all cores in a cluster are powered down the parent cluster can be also powered down. When the last core has requested powering down follow by sending the cluster power down sequence to the system power controller firmware. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I0ffeb339852c66ef62743aecd3e17ca20bad6216
2020-01-27ti: k3: common: Rename device IDs to be more consistentAndrew F. Davis
The core number is called 'core_id' but the processor and device IDs are called 'proc' and 'device'. Rename these to make them less confusing. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I3d7c6dddd7aa37b5dee1aa9689ce31730e9c3b59
2020-01-27Merge changes from topic "pie" into integrationSoby Mathew
* changes: uniphier: make all BL images completely position-independent uniphier: make uniphier_mmap_setup() work with PIE uniphier: pass SCP base address as a function parameter uniphier: set buffer offset and length for io_block dynamically uniphier: use more mmap_add_dynamic_region() for loading images bl_common: add BL_END macro uniphier: turn on ENABLE_PIE TSP: add PIE support BL2_AT_EL3: add PIE support BL31: discard .dynsym .dynstr .hash sections to make ENABLE_PIE work PIE: pass PIE options only to BL31 Build: support per-BL LDFLAGS
2020-01-27plat/arm/sgi: move topology information to board folderVijayenthiran Subramaniam
The platform topology description of the upcoming Arm's RD platforms have different topology than those listed in the sgi_topology.c file. So instead of adding platform specific topology into existing sgi_topology.c file, those can be added to respective board files. In order to maintain consistency with the upcoming platforms, move the existing platform topology description to respective board files. Change-Id: I4689c7d24cd0c75a3dc234370c34a85c08598abb Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
2020-01-27Merge "plat/sgm: Always use SCMI for SGM platforms" into integrationManish Pandey
2020-01-24Merge "xilinx: Unify Platform specific defines for PSCI module" into integrationMark Dykes
2020-01-24plat/sgm: Always use SCMI for SGM platformsChris Kay
As on SGI platforms, SCPI is unsupported on SGM platforms. Change-Id: I556ed095b9eb55b72447230ee2725d3c76160a08 Signed-off-by: Chris Kay <chris.kay@arm.com>
2020-01-24xilinx: Unify Platform specific defines for PSCI moduleDeepika Bhavnani
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I76f5535f1cbdaf3fc1235cd824111d9afe8f7e1b
2020-01-24uniphier: make all BL images completely position-independentMasahiro Yamada
This platform supports multiple SoCs. The next SoC will still keep quite similar architecture, but the memory base will be changed. The ENABLE_PIE improves the maintainability and usability. You can reuse a single set of BL images for other SoC/board without re-compiling TF-A at all. This will also keep the code cleaner because it avoids #ifdef around various base addresses. By defining ENABLE_PIE, BL2_AT_EL3, BL31, and BL32 (TSP) are really position-independent now. You can load them anywhere irrespective of their link address. Change-Id: I8d5e3124ee30012f5b3bfa278b0baff8efd2fff7 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-01-24uniphier: make uniphier_mmap_setup() work with PIEMasahiro Yamada
BL2_BASE, BL31_BASE, and BL32_BASE are defined in platform_def.h, that is, determined at link-time. On the other hand, BL2_END, BL31_END, and BL32_END are derived from the symbols produced by the linker scripts. So, they are fixed-up at run-time if ENABLE_PIE is enabled. To make it work in a position-indepenent manner, use BL_CODE_BASE and BL_END, both of which are relocatable. Change-Id: Ic179a7c60eb64c5f3024b178690b3ac7cbd7521b Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-01-24uniphier: pass SCP base address as a function parameterMasahiro Yamada
Currently, UNIPHIER_SCP_BASE is hard-coded in uniphier_scp_start(), which is not handy for PIE. Towards the goal of making this really position-independent, pass in image_info->image_base. Change-Id: I88e020a1919c607b1d5ce70b116201d95773bb63 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-01-24uniphier: set buffer offset and length for io_block dynamicallyMasahiro Yamada
Currently, the .buffer field in io_block_dev_spec is statically set, which is not handy for PIE. Towards the goal of making this really position-independent, set the buffer length and length in the uniphier_io_block_setup() function. Change-Id: I22b20d7b58d6ffd38f64f967a2820fca4bd7dade Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-01-24uniphier: use more mmap_add_dynamic_region() for loading imagesMasahiro Yamada
Currently, uniphier_bl2_mmap hard-codes the memory region needed for loading other images. Towards the goal of making this really position-independent, call mmap_add_dynamic_region() before that region gets accessed. Change-Id: Ieb505b91ccf2483e5f1a280accda564b33f19f11 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-01-24uniphier: turn on ENABLE_PIEMasahiro Yamada
Now that various issues in the PIE support have been fixed, this platform can enable ENABLE_PIE. I tested BL2_AT_EL3, BL31, TSP, and all of them worked. Change-Id: Ibc499c6bad30b7f81a42bfa7e435ce25f820bd9c Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-01-24ti: Unify Platform specific defines for PSCI moduleDeepika Bhavnani
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Ia7072d82116b03904c1b3982f37d96347203e621
2020-01-24st: Unify Platform specific defines for PSCI moduleDeepika Bhavnani
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I3421336230981d4cda301fa2cef24b94b08353b1
2020-01-24layerscape: Unify Platform specific defines for PSCI moduleDeepika Bhavnani
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Ib9f97be1972405e54dc9550266f5b8a6a55b93bf
2020-01-24qemu: Unify Platform specific defines for PSCI moduleDeepika Bhavnani
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I460b35f5a4ec47b13d4e811bb20881ce314e9259
2020-01-24socionext: Unify Platform specific defines for PSCI moduleDeepika Bhavnani
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Iad91e99e9d13254de23eb10e5f655253f253cf0d
2020-01-24mediatek: Unify Platform specific defines for PSCI moduleDeepika Bhavnani
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Iee98ded027c049d9f12d4bb5888c0496b3251b4e
2020-01-24intel: Unify Platform specific defines for PSCI moduleDeepika Bhavnani
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: Id3d3efc7e7711d19f0223da823713b8390ad2f47
2020-01-24marvell: Unify Platform specific defines for PSCI moduleDeepika Bhavnani
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I7d660d5a9d7e44601353c77e9b6ee4096a277d76
2020-01-24rockchip: Unify Platform specific defines for PSCI moduleDeepika Bhavnani
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I624c15d569db477506a74964bc828e1a932181d4
2020-01-24allwinner: Unify Platform specific defines for PSCI moduleDeepika Bhavnani
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I7aea86891e54522c88af5ff16795a575f9a9322d
2020-01-24imx: Unify Platform specific defines for PSCI moduleDeepika Bhavnani
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I8b19e833a4e1067e1cfcc9bfaede7854e0e63004
2020-01-24hisilicon: Unify Platform specific defines for PSCI moduleDeepika Bhavnani
PLATFORM_CORE_COUNT - Unsigned int PLATFORM_CLUSTER_COUNT - Unsigned int PLATFORM_MAX_CPUS_PER_CLUSTER - Unsigned int PLATFORM_CORE_COUNT_PER_CLUSTER - Unsigned int Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com> Change-Id: I327a8a2ab0f0e49bd62f413296c3b326393422b6
2020-01-24Merge changes from topic "tegra-downstream-01202020" into integrationSoby Mathew
* changes: Tegra194: mce: remove unused NVG functions Tegra194: support for NVG interface v6.6 Tegra194: smmu: add PCIE0R1 mc reg to system suspend save list Tegra194: enable driver for general purpose DMA engine Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms Tegra194: organize the memory/mmio map to make it linear Tegra194: memctrl: enable mc sid OVERRIDE for PCIE0R1 Tegra194: support for boot params wider than 32-bits Tegra194: memctrl: set reorder depth limit for PCIE blocks Tegra194: memctrl: program MC_TXN_OVERRIDE reg for PTCR, MPCORE and MIU Tegra194: memctrl: set CGID_TAG_ADR instead of CGID_TAG_DEFAULT Tegra194: memctrl: update mss reprogramming as HW PROD settings Tegra194: memctrl: Disable PVARDC coalescer Tegra194: memctrl: force seswr/rd transactions as passsthru & coherent Tegra194: Request CG7 from last core in cluster Tegra194: toggle SE clock during context save/restore Tegra: bpmp: fix header file paths
2020-01-24Merge "Prevent speculative execution past ERET" into integrationSoby Mathew
2020-01-24Merge "Xilinx zynqmp: add missing pin control group for ethernet 0." into ↵Manish Pandey
integration
2020-01-23Merge changes from topic "bridge-en" into integrationManish Pandey
* changes: intel: Add function to check fpga readiness intel: Add bridge control for FPGA reconfig intel: FPGA config_isdone() status query intel: System Manager refactoring intel: Refactor reset manager driver intel: Enable bridge access in Intel platform intel: Modify non secure access function
2020-01-23Merge "xilinx: versal: PLM to ATF handover" into integrationAlexei Fedorov
2020-01-23Merge "xilinx: common: Move ATF handover to common file" into integrationAlexei Fedorov
2020-01-23Tegra194: mce: remove unused NVG functionsVarun Wadekar
This patch removes unused functions from the NVG driver. * nvg_enable_power_perf_mode * nvg_disable_power_perf_mode * nvg_enable_power_saver_modes * nvg_disable_power_saver_modes * nvg_roc_clean_cache * nvg_roc_flush_cache Change-Id: I0387a40dec35686deaad623a8350de89acfe9393 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-01-23Tegra194: support for NVG interface v6.6Varun Wadekar
This patch updates the NVG interface header file to v6.6. Change-Id: I2f5df274bf820ba1c5df47d8dcbf7f5f056ff45f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2020-01-23Tegra194: smmu: add PCIE0R1 mc reg to system suspend save listPritesh Raithatha
PCIE0R1 security and override registers need to be preserved across system suspend. Adding them to system suspend save register list. Due to addition of above registers, increasing context save memory by 2 bytes. Change-Id: I1b3a56aee31f3c11e3edc2fb0a6da146eec1a30d Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
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