From 093ba62e14099ab4bd9c2452044d19e3589925d6 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Fri, 21 Aug 2020 10:47:17 +0800 Subject: doc: Correct CPACR.FPEN usage To avoid trapping from EL0/1, FPEN bits need to be set 0x3, not clearing. Signed-off-by: Peng Fan Change-Id: Ic34e9aeb876872883c5f040618ed6d50f21dacd0 --- docs/design/firmware-design.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'docs') diff --git a/docs/design/firmware-design.rst b/docs/design/firmware-design.rst index a357d5858..c12e73f45 100644 --- a/docs/design/firmware-design.rst +++ b/docs/design/firmware-design.rst @@ -369,7 +369,7 @@ Architectural initialization For AArch64, BL2 performs the minimal architectural initialization required for subsequent stages of TF-A and normal world software. EL1 and EL0 are given -access to Floating Point and Advanced SIMD registers by clearing the +access to Floating Point and Advanced SIMD registers by setting the ``CPACR.FPEN`` bits. For AArch32, the minimal architectural initialization required for subsequent -- cgit v1.2.3