From d7b08e69044611c13f2691011a0dc02383106474 Mon Sep 17 00:00:00 2001 From: johpow01 Date: Fri, 29 May 2020 14:17:38 -0500 Subject: Workaround for Cortex A76 erratum 1791580 Cortex A76 erratum 1791580 is a Cat B erratum present in earlier revisions of the Cortex A76. The workaround is to set a bit in the implementation defined CPUACTLR2 register, which forces atomic store operations to write-back memory to be performed in the L1 data cache. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell Change-Id: Iefd58159b3f2e2286138993317b98e57dc361925 --- docs/design/cpu-specific-build-macros.rst | 3 +++ 1 file changed, 3 insertions(+) (limited to 'docs') diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 591f2f886..53da6885a 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -227,6 +227,9 @@ For Cortex-A76, the following errata build flags are defined : - ``ERRATA_A76_1275112``: This applies errata 1275112 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r3p0 of the CPU. +- ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 + CPU. This needs to be enabled only for revision <= r4p0 of the CPU. + For Cortex-A78, the following errata build flags are defined : - ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 -- cgit v1.2.3 From dcbfbcb5de2c0110cf397dae62a4f6cf7ad2a6a2 Mon Sep 17 00:00:00 2001 From: johpow01 Date: Tue, 2 Jun 2020 15:02:28 -0500 Subject: Workaround for Cortex A76 erratum 1800710 Cortex A76 erratum 1800710 is a Cat B erratum, present in older revisions of the Cortex A76 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell Change-Id: Ifc34f2e9e053dcee6a108cfb7df7ff7f497c9493 --- docs/design/cpu-specific-build-macros.rst | 3 +++ 1 file changed, 3 insertions(+) (limited to 'docs') diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 53da6885a..264d0c688 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -230,6 +230,9 @@ For Cortex-A76, the following errata build flags are defined : - ``ERRATA_A76_1791580``: This applies errata 1791580 workaround to Cortex-A76 CPU. This needs to be enabled only for revision <= r4p0 of the CPU. +- ``ERRATA_A76_1800710``: This applies errata 1800710 workaround to Cortex-A76 + CPU. This needs to be enabled only for revision <= r4p0 of the CPU. + For Cortex-A78, the following errata build flags are defined : - ``ERRATA_A78_1688305``: This applies errata 1688305 workaround to Cortex-A78 -- cgit v1.2.3