From 8913047a52e646877812617a2d98cff99494487b Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Tue, 27 Jul 2021 00:39:40 -0700 Subject: feat(cpus): workaround for Cortex A78 AE erratum 1951502 Cortex A78 AE erratum 1951502 is a Cat B erratum that applies to revisions <= r0p1. It is still open. This erratum is avoided by inserting a DMB ST before acquire atomic instructions without release semantics through a series of writes to implementation defined system registers. SDEN is available at https://developer.arm.com/documentation/SDEN1707912/0900 Change-Id: I812c5a37cdd03486df8af6046d9fa988f6a0a098 Signed-off-by: Varun Wadekar --- lib/cpus/aarch64/cortex_a78_ae.S | 89 +++++++++++++++++++++++++++++++++++----- lib/cpus/cpu-ops.mk | 10 ++++- 2 files changed, 88 insertions(+), 11 deletions(-) (limited to 'lib/cpus') diff --git a/lib/cpus/aarch64/cortex_a78_ae.S b/lib/cpus/aarch64/cortex_a78_ae.S index 9aff9ac85..c8cccf278 100644 --- a/lib/cpus/aarch64/cortex_a78_ae.S +++ b/lib/cpus/aarch64/cortex_a78_ae.S @@ -1,5 +1,6 @@ /* * Copyright (c) 2019-2020, ARM Limited. All rights reserved. + * Copyright (c) 2021, NVIDIA Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -16,12 +17,73 @@ #error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled" #endif +/* -------------------------------------------------- + * Errata Workaround for A78 AE Erratum 1951502. + * This applies to revisions r0p0 and r0p1 of A78 AE. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------- + */ +func errata_a78_ae_1951502_wa + /* Compare x0 against revisions r0p0 - r0p1 */ + mov x17, x30 + bl check_errata_1951502 + cbz x0, 1f + + msr S3_6_c15_c8_0, xzr + ldr x0, =0x10E3900002 + msr S3_6_c15_c8_2, x0 + ldr x0, =0x10FFF00083 + msr S3_6_c15_c8_3, x0 + ldr x0, =0x2001003FF + msr S3_6_c15_c8_1, x0 + + mov x0, #1 + msr S3_6_c15_c8_0, x0 + ldr x0, =0x10E3800082 + msr S3_6_c15_c8_2, x0 + ldr x0, =0x10FFF00083 + msr S3_6_c15_c8_3, x0 + ldr x0, =0x2001003FF + msr S3_6_c15_c8_1, x0 + + mov x0, #2 + msr S3_6_c15_c8_0, x0 + ldr x0, =0x10E3800200 + msr S3_6_c15_c8_2, x0 + ldr x0, =0x10FFF003E0 + msr S3_6_c15_c8_3, x0 + ldr x0, =0x2001003FF + msr S3_6_c15_c8_1, x0 + + isb +1: + ret x17 +endfunc errata_a78_ae_1951502_wa + +func check_errata_1951502 + /* Applies to revisions r0p0 and r0p1. */ + mov x1, #CPU_REV(0, 0) + mov x2, #CPU_REV(0, 1) + b cpu_rev_var_range +endfunc check_errata_1951502 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A78-AE * ------------------------------------------------- */ -#if ENABLE_AMU func cortex_a78_ae_reset_func + mov x19, x30 + bl cpu_get_rev_var + mov x18, x0 + +#if ERRATA_A78_AE_1951502 + mov x0, x18 + bl errata_a78_ae_1951502_wa +#endif + +#if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT @@ -39,11 +101,12 @@ func cortex_a78_ae_reset_func /* Enable group1 counters */ mov x0, #CORTEX_A78_AMU_GROUP1_MASK msr CPUAMCNTENSET1_EL0, x0 +#endif + isb - ret + ret x19 endfunc cortex_a78_ae_reset_func -#endif /* ------------------------------------------------------- * HW will do the cache maintenance while powering down @@ -66,6 +129,18 @@ endfunc cortex_a78_ae_core_pwr_dwn */ #if REPORT_ERRATA func cortex_a78_ae_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502 + + ldp x8, x30, [sp], #16 ret endfunc cortex_a78_ae_errata_report #endif @@ -89,12 +164,6 @@ func cortex_a78_ae_cpu_reg_dump ret endfunc cortex_a78_ae_cpu_reg_dump -#if ENABLE_AMU -#define A78_AE_RESET_FUNC cortex_a78_ae_reset_func -#else -#define A78_AE_RESET_FUNC CPU_NO_RESET_FUNC -#endif - declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \ - A78_AE_RESET_FUNC, \ + cortex_a78_ae_reset_func, \ cortex_a78_ae_core_pwr_dwn diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 050a56e4f..b36616760 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -1,6 +1,6 @@ # # Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved. -# Copyright (c) 2020, NVIDIA Corporation. All rights reserved. +# Copyright (c) 2020-2021, NVIDIA Corporation. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -311,6 +311,10 @@ ERRATA_A78_1941498 ?=0 # well but there is no workaround for that revision. ERRATA_A78_1951500 ?=0 +# Flag to apply erratum 1951502 workaround during reset. This erratum applies +# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open. +ERRATA_A78_AE_1951502 ?=0 + # Flag to apply erratum 1821534 workaround during reset. This erratum applies # to revisions r0p0 and r1p0 of the A78 cpu. ERRATA_A78_1821534 ?=0 @@ -646,6 +650,10 @@ $(eval $(call add_define,ERRATA_A78_1941498)) $(eval $(call assert_boolean,ERRATA_A78_1951500)) $(eval $(call add_define,ERRATA_A78_1951500)) +# Process ERRATA_A78_AE_1951502 flag +$(eval $(call assert_boolean,ERRATA_A78_AE_1951502)) +$(eval $(call add_define,ERRATA_A78_AE_1951502)) + # Process ERRATA_A78_1821534 flag $(eval $(call assert_boolean,ERRATA_A78_1821534)) $(eval $(call add_define,ERRATA_A78_1821534)) -- cgit v1.2.3